Craig Topper 042394b69e [RISCV] Add a command line option to control the LMUL used by TTI's getRegisterBitWidth. ...

By default we return the width of an LMUL=1 register. We can enable
testing with larger LMUL values by returning a larger bit width.

This patch adds a RISCV specific option to provide a LMUL which will be
multiplied by the LMUL=1 bit width.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D116339

2022-01-07 20:02:10 -08:00

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lit.local.cfg

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masked_gather_scatter.ll

[LV] Update test that was missed in e844f05397.

2021-10-18 18:23:00 +01:00

riscv-interleaved.ll

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riscv-unroll.ll

[RISCV] Add a command line option to control the LMUL used by TTI's getRegisterBitWidth.

2022-01-07 20:02:10 -08:00

scalable-reductions.ll

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scalable-vf-hint.ll

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unroll-in-loop-vectorizer.ll

[RISCV] Disable interleaving scalar loops in the loop vectorizer.

2021-12-23 08:37:24 -06:00