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7cc200529f5791ceed510a02c0fa5343d535267d
clang-p2996/llvm/test/CodeGen/RISCV
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Iris Shi 1e503d08e1 [RISCV][MC] Add support for Q extension (#139369) 
Closes #130217.

https://github.com/riscv/riscv-isa-manual/blob/main/src/q-st-ext.adoc
2025-05-15 10:51:06 +08:00
..
GlobalISel
GlobalISel: Translate minimumnum and maximumnum (#139106)
2025-05-08 20:03:34 +02:00
intrinsics
…
rvv
[RISCV] Support LLVM IR intrinsics for XAndesVPackFPH (#139860)
2025-05-15 10:21:27 +08:00
abds-neg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
abds.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
abdu-neg.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
abdu.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
add_sext_shl_constant.ll
[RISCV] Added test case for PR119527. NFC (#121816)
2025-01-07 13:33:22 -03:00
add_shl_constant.ll
[RISCV] Don't commute with shift if it would break sh{1,2,3}add pattern (#119527)
2025-01-06 19:23:21 +08:00
add-before-shl.ll
[RISCV,test] Replace -riscv-no-aliases with -M no-aliases
2025-04-08 19:42:43 -07:00
add-imm64-to-sub.ll
[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)
2025-05-13 09:12:24 +02:00
add-imm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll
…
addrspacecast.ll
…
aext-to-sext.ll
…
aext.ll
…
align-loops.ll
…
align.ll
…
alloca.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
allow-check.ll
…
alu8.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
alu16.ll
…
alu32.ll
…
alu64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
analyze-branch.ll
…
and-add-lsr.ll
…
and-shl.ll
[RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) (#119567)
2024-12-12 07:58:36 +01:00
and.ll
…
arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomic-fence.ll
…
atomic-load-store.ll
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
atomic-load-zext.ll
[RISCV] Remove AND mask generated by ( zext ( atomic_load ) ) by replacing the load with zextload for orderings not stronger then monotonic. (#136502)
2025-04-28 08:35:51 -07:00
atomic-rmw-discard.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
atomic-rmw-sub.ll
…
atomic-rmw.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomic-signext.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomicrmw-cond-sub-clamp.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
atomicrmw-uinc-udec-wrap.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
attributes-module-flag.ll
…
attributes.ll
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
avgceils.ll
…
avgceilu.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
avgfloors.ll
…
avgflooru.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
bf16-promote.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bfloat-arith.ll
…
bfloat-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
bfloat-convert.ll
[RISCV][LibCall] Add libcall for i64 -> bf16 (#130024)
2025-03-07 09:23:50 +08:00
bfloat-fcmp.ll
…
bfloat-frem.ll
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bfloat-imm.ll
…
bfloat-isnan.ll
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bfloat-mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bfloat-select-fcmp.ll
…
bfloat-select-icmp.ll
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bfloat.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bitextract-mac.ll
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bitreverse-shift.ll
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bittest.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
blockaddress.ll
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branch_zero.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
branch-on-zero.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
branch-opt.ll
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branch-opt.mir
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branch-relaxation-rv32.ll
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branch-relaxation-rv32e.ll
[RISCV] Use X9 instead of X27 in RISCVInstrInfo::insertIndirectBranch for RVE (#139214)
2025-05-09 08:41:14 -07:00
branch-relaxation-rv64.ll
…
branch.ll
…
bswap-bitreverse.ll
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bswap-shift.ll
[RISCV] Remove the TODO for folding bswap and shift from the test. (NFC) (#129972)
2025-03-06 13:02:17 +08:00
byval.ll
…
callee-saved-fpr32s.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
callee-saved-fpr64s.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
callee-saved-gprs.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
calling-conv-half.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32-ilp32f-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32d.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32e.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-ilp32f-ilp32d-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-lp64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-rv32f-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-rv32f-ilp32e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-sext-zext.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
calling-conv-vector-float.ll
…
calling-conv-vector-on-stack.ll
…
calls.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
clear-cache.ll
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cm_mvas_mvsa.ll
…
cm_mvas_mvsa.mir
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cmov-branch-opt.ll
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cmp-bool.ll
…
codemodel-lowering.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
compress-double.ll
…
compress-float.ll
…
compress-inline-asm.ll
…
compress-opt-branch.ll
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compress-opt-select.ll
[llc] Add -M for InstPrinter options
2025-04-08 19:34:03 -07:00
compress.ll
…
condbinops.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
condops.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
convert-highly-predictable-select-to-branch.ll
…
copy-frameindex.mir
…
copyprop.ll
…
copysign-casts.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
csr-first-use-cost.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
ctlz-cttz-ctpop.ll
[CGP] Despeculate ctlz/cttz with "illegal" integer types (#137197)
2025-04-29 22:33:40 +03:00
ctz_zero_return_test.ll
[ARM][RISCV] Partially revert #101786 (#137120)
2025-04-24 10:13:05 +03:00
debug-line.ll
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
di-assignment-tracking-vector.ll
[DebugInfo] Handle additional types of stores in assignment tracking (#129070)
2025-04-22 17:14:25 +01:00
disable-tail-calls.ll
…
disjoint.ll
…
div_minsize.ll
…
div-by-constant.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
div-pow2.ll
…
div.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
double_reduct.ll
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double-arith-strict.ll
…
double-arith.ll
…
double-bitmanip-dagcombines.ll
…
double-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
double-calling-conv.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-convert-strict.ll
…
double-convert.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
double-fcmp-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-fcmp.ll
…
double-frem.ll
…
double-imm.ll
[RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). (#133200)
2025-03-27 07:45:42 -07:00
double-intrinsics-strict.ll
…
double-intrinsics.ll
[RISCV] Remove the TODO for fmaximum/fminimum from the tests. (NFC) (#129969)
2025-03-06 13:01:58 +08:00
double-isnan.ll
…
double-maximum-minimum.ll
[RISCV] Remove unused check prefixes from double maximum/minimum test. NFC
2025-03-17 16:39:51 +08:00
double-mem.ll
[RISCV] Add isel patterns to use Zilsd for f64 load/store for Zdinx on RV32. (#139935)
2025-05-14 12:19:38 -07:00
double-previous-failure.ll
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double-round-conv-sat.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-round-conv.ll
…
double-select-fcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-select-icmp.ll
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double-stack-spill-restore.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-zfa.ll
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dso_local_equivalent.ll
AsmPrinter: Remove ELF's special lowerRelativeReference for unnamed_addr function; use lowerDSOLocalEquivalent in more cases
2025-04-08 10:11:20 -07:00
dwarf-eh.ll
…
early-clobber-tied-def-subreg-liveness.ll
[RISCV] Refine location size for segment spill and fill (#133268)
2025-03-28 07:06:17 -07:00
eh-dwarf-cfa.ll
…
elf-preemption.ll
…
emit-x8-as-fp.ll
[RISCV][MC] Emit x8 as fp instead of s0 (#135500)
2025-04-14 14:48:47 +08:00
emutls.ll
…
exception-pointer-register.ll
…
fastcc-bf16.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-float.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-half.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-int.ll
…
fastcc-without-f-reg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
features-info.ll
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
fixed-csr.ll
…
fixups-diff.ll
…
fli-licm.ll
…
float-arith-strict.ll
…
float-arith.ll
…
float-bit-preserving-dagcombines.ll
…
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
float-convert-strict.ll
…
float-convert.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
float-fcmp-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
float-fcmp.ll
…
float-frem.ll
…
float-imm.ll
…
float-intrinsics-strict.ll
…
float-intrinsics.ll
[RISCV] Remove the TODO for fmaximum/fminimum from the tests. (NFC) (#129969)
2025-03-06 13:01:58 +08:00
float-isnan.ll
…
float-maximum-minimum.ll
…
float-mem.ll
…
float-round-conv-sat.ll
…
float-round-conv.ll
…
float-select-fcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
float-select-icmp.ll
…
float-select-verify.ll
…
float-zfa.ll
…
flt-rounds.ll
…
fmax-fmin.ll
…
fold-addi-loadstore.ll
[RISCV] Don't fold offsets into auipc if offset is larger than the reference global variable. (#135297)
2025-04-11 16:12:19 -07:00
fold-binop-into-select-return-constant.ll
…
fold-binop-into-select.ll
…
fold-mem-offset.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
fold-mem-offset.mir
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
forced-atomics.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fp16-promote.ll
…
fp128.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fp-fcanonicalize.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fpclamptosat.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fpenv.ll
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frame-info.ll
…
frame.ll
…
frameaddr-returnaddr.ll
…
frm-dependency.ll
[RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). (#133200)
2025-03-27 07:45:42 -07:00
frm-write-in-loop.ll
[RISCV] Explicitly set FRM defs as non-dead to prevent their reordering with instructions that may use it (#135176)
2025-04-11 15:07:51 +03:00
get-register-invalid.ll
…
get-register-noreserve.ll
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get-register-reserve.ll
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get-setcc-result-type.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
ghccc-nest.ll
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ghccc-rv32.ll
…
ghccc-rv64.ll
…
ghccc-without-f-reg.ll
…
global-merge-minsize-smalldata-nonzero.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-minsize-smalldata-zero.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-minsize.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-offset.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
graalcc.ll
…
half-arith-strict.ll
[RISCV] Remove unused check prefixes from half arith strict test. NFC
2025-03-17 12:51:39 +08:00
half-arith.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-bitmanip-dagcombines.ll
…
half-br-fcmp.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
half-convert-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-convert.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
half-fcmp-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-fcmp.ll
…
half-frem.ll
…
half-imm.ll
…
half-intrinsics.ll
[RISCV] Remove the TODO for fmaximum/fminimum from the tests. (NFC) (#129969)
2025-03-06 13:01:58 +08:00
half-isnan.ll
…
half-maximum-minimum.ll
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half-mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-round-conv-sat.ll
…
half-round-conv.ll
…
half-select-fcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-select-icmp.ll
…
half-zfa-fli.ll
…
half-zfa.ll
…
hoist-global-addr-base.ll
…
hwasan-check-memaccess.ll
[llc] Add -M for InstPrinter options
2025-04-08 19:34:03 -07:00
i32-icmp.ll
[RISCV] Use QC_E_ADDI to improve codegen for icmp {eq, ne} with a constant (#139558)
2025-05-13 07:46:16 +05:30
i64-icmp.ll
…
iabs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
idiv_large.ll
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imm-cse.ll
…
imm.ll
[RISCV][Xqcili] Implement Load Immediate Support (#132496)
2025-03-25 07:59:44 -07:00
indirectbr.ll
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init-array.ll
…
inline-asm-abi-names.ll
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inline-asm-clobbers.ll
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inline-asm-d-abi-names.ll
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inline-asm-d-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-d-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
[RISCV] Check the VT for R and cR inline asm constraints is 2*xlen. (#137749)
2025-04-29 08:12:32 -07:00
inline-asm-mem-constraint-2.ll
…
inline-asm-mem-constraint.ll
…
inline-asm-s-constraint-error.ll
…
inline-asm-s-constraint.ll
…
inline-asm-v-constraint.ll
…
inline-asm-xsfvcp.ll
…
inline-asm-zdinx-constraint-r.ll
…
inline-asm-zfh-constraint-f.ll
…
inline-asm-zfh-modifier-N.ll
…
inline-asm-zfinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-zhinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-option-directive.ll
…
instruction-count-remark.mir
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
…
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
[RISCV] Remove X16-31 from interrupt callee saved register list for RVE+D. (#139213)
2025-05-09 08:40:27 -07:00
intrinsic-cttz-elts-vscale.ll
[RISCV] Use a precise size for MMO on scalable spill and fill (#133171)
2025-03-26 18:25:59 -07:00
intrinsic-cttz-elts.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
ipra.ll
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
isel-optnone.ll
…
jumptable-swguarded.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
jumptable.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
kcfi-isel-mir.ll
[RISCV] Add call preserved regmask to tail calls. (#122181)
2025-01-08 16:19:31 -08:00
kcfi-mir.ll
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
kcfi-patchable-function-prefix.ll
…
kcfi.ll
[RISCV,test] Replace -riscv-no-aliases with -M no-aliases
2025-04-08 19:42:43 -07:00
lack-of-signed-truncation-check.ll
…
large-stack.ll
…
legalize-fneg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
libcall-tail-calls.ll
…
lit.local.cfg
…
live-sp.mir
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
llvm.exp10.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
llvm.frexp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
load-setcc-combine.ll
…
load-store-pair.ll
[RISCV] Generate MIPS load/store pair instructions (#124717)
2025-03-07 09:21:36 +01:00
local-stack-slot-allocation.ll
…
loop-strength-reduce-add-cheaper-than-mul.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
loop-strength-reduce-loop-invar.ll
…
lpad.ll
[RISCV] Remove Last Traces of User Interrupts (#129300)
2025-03-04 11:36:16 -08:00
lsr-legaladdimm.ll
…
machine-combiner-mir.ll
…
machine-combiner-strategies.ll
…
machine-combiner.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
machine-combiner.mir
…
machine-copyprop-noop-removal.mir
[MachineCopyPropagation] Recognise and delete no-op moves produced after forwarded uses (#129889)
2025-03-10 13:22:59 +00:00
machine-copyprop-simplifyinstruction.mir
[RISCV][TII] Add and use new hook to simplify/canonicalize instructions after MachineCopyPropagation (#137973)
2025-05-08 12:33:14 +01:00
machine-cp.mir
…
machine-cse.ll
…
machine-outliner-and-machine-copy-propagation.ll
…
machine-outliner-call-x5-liveout.mir
[RISCV] [MachineOutliner] Analyze all candidates (#127659)
2025-02-21 12:53:13 +05:30
machine-outliner-call.ll
…
machine-outliner-cfi.mir
…
machine-outliner-leaf-descendants.ll
…
machine-outliner-patchable.ll
…
machine-outliner-position.mir
…
machine-outliner-throw.ll
…
machine-pipeliner.ll
[RISCV] Add software pipeliner support (#117546)
2024-12-19 13:00:08 +08:00
machine-sink-load-immediate.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
machinelicm-address-pseudos.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
machinelicm-constant-phys-reg.ll
…
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
…
machineoutliner-x5.mir
…
machineoutliner.mir
…
MachineSink-implicit-x0.mir
[CodeGen][NewPM] Port MachineSink to NPM (#115434)
2025-03-03 15:49:37 +05:30
macro-fusion-lui-addi.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
macro-fusions.mir
…
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible-zbc-zhinx.mir
…
make-compressible-zbc.mir
…
make-compressible-zfinx.mir
…
make-compressible.mir
…
mem64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memcmp-optsize.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memcpy-inline.ll
…
memcpy.ll
Reapply "[RISCV] Rework memcpy test (#120364)"
2025-01-13 12:06:26 +08:00
memmove.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memset-inline.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
memset-pattern.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
min-max.ll
…
mir-target-flags.ll
…
misched-load-clustering.ll
…
misched-mem-clustering.mir
…
misched-postra-direction.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
miss-sp-restore-eh.ll
Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)
2025-04-22 17:36:41 -04:00
module-elf-flags.ll
…
module-target-abi2.ll
…
module-target-abi3.ll
…
module-target-abi.ll
…
mul-expand.ll
[NFC][RISCV] Pre-commit tests for RVI constant multiplication expansion (#139200)
2025-05-09 11:45:14 +08:00
mul.ll
[RISCV] Add 2^N + 2^M expanding pattern for mul (#137954)
2025-05-10 11:16:39 +08:00
musttail-call.ll
…
naked-fn-with-frame-pointer.ll
…
narrow-shl-cst.ll
…
neg-abs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
nest-register.ll
…
nomerge.ll
…
nontemporal-scalable.ll
…
nontemporal.ll
…
note-gnu-property-zicfiss.ll
[RISCV] Emit .note.gnu.property section when Zicfiss-based shadow stack is enabled (#127036)
2025-05-14 11:48:59 +08:00
O0-pipeline.ll
Rename ExpandLargeFpConvertPass to ExpandFpPass (#131128)
2025-03-14 13:11:45 +01:00
O3-pipeline.ll
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
opt-w-instrs.mir
[RISCV] Add PseudoCCMOVGPRNoX0 test caes for RISCVOptWInstrs. NFC
2025-01-31 15:19:44 -08:00
option-exact-inlineasm.ll
[RISCV] Support .option {no}exact (#122483)
2025-03-26 11:14:16 -07:00
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax-relocation.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
2025-02-25 10:04:57 -08:00
orc-b-patterns.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
out-of-reach-emergency-slot.mir
…
overflow-intrinsic-optimizations.ll
…
overflow-intrinsics.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
patchable-function-entry.ll
[RISCV,test] Replace -riscv-no-aliases with -M no-aliases
2025-04-08 19:42:43 -07:00
pei-crash.ll
…
pic-models.ll
…
poison-legalization.ll
Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR." (#135056)
2025-04-10 11:29:14 -04:00
postra-copy-expand.mir
[RISCV] Attach an implicit source operand on vector copies (#126155)
2025-02-08 16:25:27 -08:00
pr40333.ll
…
pr51206.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr53662.mir
…
pr55201.ll
…
pr56110.ll
…
pr56457.ll
[ARM][RISCV] Partially revert #101786 (#137120)
2025-04-24 10:13:05 +03:00
pr58025.ll
…
pr58286.ll
…
pr58511.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr63365.ll
…
pr63816.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr64503.ll
…
pr64645.ll
…
pr64772.ll
…
pr64935.ll
…
pr65025.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
pr66603.ll
…
pr68855.ll
…
pr69586.ll
[RISCV] Use a precise size for MMO on scalable spill and fill (#133171)
2025-03-26 18:25:59 -07:00
pr80052.mir
…
pr84200.ll
…
pr84653_pr85190.ll
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
2024-12-19 21:38:20 +01:00
pr88365.ll
…
pr90652.ll
…
pr90730.ll
…
pr92193.ll
…
pr94145.ll
…
pr94265.ll
…
pr95271.ll
[ARM][RISCV] Partially revert #101786 (#137120)
2025-04-24 10:13:05 +03:00
pr95284.ll
…
pr96366.ll
…
pr97304.ll
…
pr101786.ll
[CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (#102731)
2025-04-23 08:54:10 +03:00
pr135206.ll
[RISCV] Fix assertion failure when using -fstack-clash-protection (#135248)
2025-04-18 09:12:52 -07:00
prefer-w-inst.ll
…
prefer-w-inst.mir
…
prefetch.ll
…
prolog-epilogue.ll
…
push-pop-opt-crash.ll
[RISCV] Update unrelated bad code from test case
2025-03-19 11:09:49 -07:00
push-pop-popret.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
qci-interrupt-attr-fpr.ll
[RISCV] QCI Interrupt Support (#129957)
2025-03-06 13:31:08 -08:00
qci-interrupt-attr.ll
[RISCV] Support Push/Pop with Xqci (#134191)
2025-04-28 08:12:45 -07:00
rda-stack.mir
[ReachingDefAnalysis] Fix management of MBBFrameObjsReachingDefs (#124943)
2025-02-04 10:04:19 -05:00
readcyclecounter.ll
…
readsteadycounter.ll
…
reassoc-shl-addi-add.ll
[RISCV] Add combine for shadd family of instructions. (#130829)
2025-03-31 10:02:12 -04:00
reduce-unnecessary-extension.ll
…
reduction-formation.ll
…
redundant-copy-from-tail-duplicate.ll
[RISCV] Set AllocationPriority in line with LMUL (#131176)
2025-03-18 08:25:49 -07:00
regalloc-last-chance-recoloring-failure.ll
[RISCV] Refine location size for segment spill and fill (#133268)
2025-03-28 07:06:17 -07:00
relative-reloc.ll
AsmPrinter: Remove ELF's special lowerRelativeReference for unnamed_addr function; use lowerDSOLocalEquivalent in more cases
2025-04-08 10:11:20 -07:00
relax-per-target-feature.ll
…
rem.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
remat.ll
…
renamable-copy.mir
…
repeated-fp-divisors.ll
…
replace-with-veclib-sleef-scalable.ll
[RISCV][SLEEF] Fix incorrect vector function mapping for llvm.exp.f64 (#121641)
2025-05-12 13:34:46 +08:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegen-prepare-atp.ll
…
riscv-codegenprepare-asm.ll
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
riscv-codegenprepare.ll
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
riscv-func-target-feature.ll
…
riscv-tail-dup-size.ll
…
rotl-rotr.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32-fuchsia.ll
…
rv32-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
[RISCV] Remove the TODO for lowering f32 libcall on RV64 with lp64 abi. (NFC)
2025-03-07 10:52:04 +08:00
rv32i-rv64i-half.ll
…
rv32xtheadba.ll
[RISCV] Add 2^N + 2^M expanding pattern for mul (#137954)
2025-05-10 11:16:39 +08:00
rv32xtheadbb.ll
[CGP] Despeculate ctlz/cttz with "illegal" integer types (#137197)
2025-04-29 22:33:40 +03:00
rv32xtheadbs.ll
…
rv32zba.ll
[RISCV] Implement codegen for XAndesPerf lea instructions (#137925)
2025-05-12 10:41:53 +08:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
[RISCV] Sink NOT to be fold into ANDN/ORN/XNOR/VANDN (#131632)
2025-03-19 06:06:13 +01:00
rv32zbb.ll
[CGP] Despeculate ctlz/cttz with "illegal" integer types (#137197)
2025-04-29 22:33:40 +03:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32zimop-intrinsic.ll
…
rv32zknd-intrinsic-autoupgrade.ll
…
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic-autoupgrade.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic-autoupgrade.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-double-convert-strict.ll
…
rv64-double-convert.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-float-convert-strict.ll
…
rv64-float-convert.ll
…
rv64-half-convert-strict.ll
…
rv64-half-convert.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-large-stack.ll
…
rv64-patchpoint.ll
…
rv64-stackmap-args.ll
[CodeGen] @llvm.experimental.stackmap make operands immediate (#117932)
2024-12-11 17:41:19 +08:00
rv64-stackmap-frame-setup.ll
…
rv64-stackmap-nops.ll
…
rv64-stackmap.ll
…
rv64-statepoint-call-lowering-x1.ll
…
rv64-statepoint-call-lowering-x2.ll
…
rv64-statepoint-call-lowering.ll
…
rv64-trampoline.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-typepromotion.ll
…
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64e.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
…
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
…
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64xtheadba.ll
[RISCV] Add 2^N + 2^M expanding pattern for mul (#137954)
2025-05-10 11:16:39 +08:00
rv64xtheadbb.ll
[ARM][RISCV] Partially revert #101786 (#137120)
2025-04-24 10:13:05 +03:00
rv64xtheadbs.ll
…
rv64zba.ll
[RISCV] Implement codegen for XAndesPerf lea instructions (#137925)
2025-05-12 10:41:53 +08:00
rv64zbb-intrinsic.ll
…
rv64zbb-zbkb.ll
[RISCV] Sink NOT to be fold into ANDN/ORN/XNOR/VANDN (#131632)
2025-03-19 06:06:13 +01:00
rv64zbb.ll
[ARM][RISCV] Partially revert #101786 (#137120)
2025-04-24 10:13:05 +03:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
…
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
…
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
…
rv64zfhmin-half-convert.ll
…
rv64zfhmin-half-intrinsics.ll
…
rv64zimop-intrinsic.ll
…
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic-autoupgrade2.ll
…
rv64zksed-intrinsic-autoupgrade.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic-autoupgrade.ll
…
rv64zksh-intrinsic.ll
…
sadd_sat_plus.ll
…
sadd_sat.ll
…
saverestore-scs.ll
…
saverestore.ll
…
scmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
sdata-sections.ll
…
sdiv-pow2-cmov.ll
…
select-and.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-bare.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-binop-identity.ll
…
select-cc.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-const.ll
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
2025-02-25 10:04:57 -08:00
select-constant-xor.ll
[CodeGenPrepare][RISCV] Combine (X ^ Y) and (X == Y) where appropriate (#130922)
2025-04-02 09:56:09 -07:00
select-optimize-multiple.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
select-optimize-multiple.mir
…
select-or.ll
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
select-to-and-zext.ll
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select.ll
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
2025-02-25 10:04:57 -08:00
selectcc-to-shiftand.ll
[RISCV] Remove the FIXME for using sraiw+and. NFC.
2025-04-22 09:13:11 +08:00
setcc-logic.ll
…
sext-zext-trunc.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
sextw-removal-debug.mir
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sextw-removal.ll
[ARM][RISCV] Partially revert #101786 (#137120)
2025-04-24 10:13:05 +03:00
shadowcallstack.ll
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shift-amount-mod.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
shift-and.ll
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shift-masked-shamt.ll
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shifts.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
shl-cttz.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
shl-demanded.ll
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shlimm-addimm.ll
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short-forward-branch-opt.ll
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shrinkwrap-jump-table.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
shrinkwrap.ll
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sifive7-enable-intervals.mir
[MISched] Unify the way to specify scheduling direction (#119518)
2024-12-12 11:24:07 +08:00
sifive-interrupt-attr-err.ll
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
sifive-interrupt-attr.ll
[RISCV] Fix Defs/Uses for SiFive CLIC Support (#137724)
2025-04-28 19:35:11 -07:00
signbit-test.ll
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signed-truncation-check.ll
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simplify-condbr.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
sink-and-fold-crash.mir
…
sink-icmp.ll
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spill-fill-fold.ll
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spill-fpr-scalar.ll
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spir-kernel-cc.ll
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split-offsets.ll
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
split-sp-adjust.ll
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split-store.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
split-udiv-by-constant.ll
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split-urem-by-constant.ll
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srem-lkk.ll
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srem-seteq-illegal-types.ll
[RISCV] Lower BUILD_VECTOR with i64 type to VID on RV32 if possible (#132339)
2025-04-09 13:33:58 +08:00
srem-vector-lkk.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
srodata.ll
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ssub_sat_plus.ll
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ssub_sat.ll
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stack-clash-prologue-nounwind.ll
[RISCV] Compute liveins for new basic blocks in emitStackProbeInline.
2024-12-10 12:37:45 -08:00
stack-clash-prologue.ll
[RISCV] Stack clash protection for dynamic alloca (#122508)
2025-01-16 11:58:42 -08:00
stack-folding.ll
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stack-guard-global.ll
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stack-guard-tls.ll
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stack-inst-compress.mir
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
stack-offset.ll
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stack-protector-target.ll
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stack-realignment-with-variable-sized-objects.ll
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stack-realignment.ll
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stack-slot-coloring.mir
[win] NFC: Rename EHCatchret to EHCont to allow for EH Continuation targets that aren't catchret instructions (#129953)
2025-03-06 09:28:44 -08:00
stack-slot-size.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
stack-store-check.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
subtarget-features-std-ext.ll
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switch-width.ll
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tagged-globals.ll
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tail-calls.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
target-abi-invalid.ll
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target-abi-valid.ll
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thread-pointer.ll
…
tls-models.ll
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tlsdesc-symbol.ll
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trunc-free.ll
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trunc-nsw-nuw.ll
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typepromotion-overflow.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
uadd_sat_plus.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
uadd_sat.ll
…
ucmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
umulo-128-legalisation-lowering.ll
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unaligned-load-store.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
unfold-masked-merge-scalar-variablemask.ll
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unroll-loop-cse.ll
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urem-lkk.ll
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urem-seteq-illegal-types.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
urem-vector-lkk.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
usub_sat_plus.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
usub_sat.ll
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vararg-ilp32e.ll
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vararg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
varargs-with-fp-and-second-adj.ll
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vector-abi.ll
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vector-tuple-zeroinitializer.ll
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verify-instr.mir
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vlenb.ll
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vscale-demanded-bits.ll
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wide-mem.ll
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wide-scalar-shift-by-byte-multiple-legalization.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
wide-scalar-shift-legalization.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
xaluo.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
xcvalu.ll
[RISCV] Rename XCValu intrinsic name *_slet(u) to *_sle(u)) (#138498)
2025-05-06 09:57:07 +08:00
xcvbi.ll
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xcvbitmanip.ll
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xcvmac.ll
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xcvmem-heuristic.ll
[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533)
2024-12-31 10:56:28 +08:00
xcvmem.ll
RISCV: Convert test to opaque pointers
2025-04-07 23:45:54 +07:00
xqccmp_mvas_mvsa.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-additional-stack.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqccmp-callee-saved-gprs.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqccmp-cm-popretz.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-cm-push-pop.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-push-pop-popret.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqccmp-with-float.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
xqcia.ll
[RISCV] Add ISel patterns for Xqcia instructions (#136548)
2025-04-22 15:40:03 +05:30
xqcilia.ll
[RISCV] Add ISel patterns for Xqcilia instructions (#135724)
2025-04-16 06:48:56 +05:30
xqcilo.ll
[RISCV] Add basic ISel patterns for Xqcilo instructions (#135901)
2025-04-16 11:19:13 +05:30
xqcisls.ll
[RISCV] Add basic ISel patterns for Xqcisls instructions (#135918)
2025-04-16 13:10:56 +05:30
xray-attribute-instrumentation.ll
[XRay][RISCV] RISCV support for XRay (#117368)
2024-12-10 17:57:04 -08:00
xtheadfmemidx.ll
…
xtheadmac.ll
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xtheadmemidx.ll
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
xtheadmempair.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zalasr-offset-folding.ll
[RISCV] Return false for Zalasr load/store in isWorthFoldingAdd. (#136799)
2025-04-23 14:47:42 -07:00
zbb-cmp-combine.ll
[RISCV][test] Fix a comment typo (#134242)
2025-04-07 20:47:21 +02:00
zbb-logic-neg-imm.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
zcb-regalloc-hints.ll
[RISCV][MC] Enable printing of zext.b alias (#133502)
2025-03-28 19:23:56 +00:00
zcmp-additional-stack.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
zcmp-cm-popretz.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
zcmp-cm-push-pop.mir
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
zcmp-prolog-epilog-crash.mir
…
zcmp-with-float.ll
Revert "[RISCV] Allow spilling to unused Zcmp Stack (#125959)" (#137060)
2025-04-23 17:36:00 -07:00
zdinx-asm-constraint.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zdinx-boundary-check.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zdinx-large-spill.mir
[RISCV] Tweak zdinx-large-spill.mir so it tests what it was intended to. NFC
2025-05-14 12:35:49 -07:00
zdinx-memoperand.ll
[RISCV] Support multiple memory operands in expandRV32ZdinxStore.
2025-01-27 22:10:51 -08:00
zext-with-load-is-free.ll
[RISCV] Remove the TODO that lbu and lhu should be selected to avoid the unnecessary masking. NFC.
2025-04-21 11:02:04 +08:00
zfh-half-intrinsics-strict.ll
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zfh-half-intrinsics.ll
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zfhmin-half-intrinsics-strict.ll
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zfhmin-half-intrinsics.ll
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zfhmin-imm.ll
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zicfilp-indirect-branch.ll
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zilsd.ll
[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808)
2025-05-14 09:54:07 -07:00
zmmul.ll
…