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7d2b9fafabd6f1a67e05ab2fa0abb5f7c8a451e7
clang-p2996/llvm/lib/Target/RISCV
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Craig Topper 4f5f38bdab [RISCV] Add early out to generateInstSeq when the initial sequence is 1 or 2 instructions. 
This avoids checking the size of the sequence repeatedly for each
special case. Especially on RV32 where none of the special cases
apply.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D152300
2023-06-06 13:23:17 -07:00
..
AsmParser
[RISCV] Don't persist invalid feature state on .option arch error
2023-06-06 20:15:12 +01:00
Disassembler
[RISCV][NFC] Simplify decoding code of disassembler
2023-05-25 15:24:41 +08:00
GISel
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
2023-06-02 23:14:17 -07:00
MCA
[llvm-mca][RISCV] Fix llvm-mca RISCVInstrument memory leak
2023-05-22 10:36:41 -07:00
MCTargetDesc
[RISCV] Add early out to generateInstSeq when the initial sequence is 1 or 2 instructions.
2023-06-06 13:23:17 -07:00
TargetInfo
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
CMakeLists.txt
Split out CodeGenTypes from CodeGen for LLT/MVT
2023-05-03 00:13:20 +09:00
RISCV.h
[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.
2023-05-01 12:05:18 -07:00
RISCV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVAsmPrinter.cpp
[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.
2023-05-01 12:05:18 -07:00
RISCVCallingConv.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVCodeGenPrepare.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add new lga pseudoinstruction
2023-05-31 18:48:21 +01:00
RISCVFeatures.td
Revert "[RISCV] Add Zvfhmin extension for clang."
2023-05-31 10:17:11 -07:00
RISCVFrameLowering.cpp
[RISCV] Make SCS prologue interrupt safe on RISC-V
2023-04-26 15:58:09 +00:00
RISCVFrameLowering.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVGatherScatterLowering.cpp
[RISCVGatherScatterLowering] Use InstSimplifyFolder
2023-05-12 17:33:07 -07:00
RISCVInsertVSETVLI.cpp
[RISCV][InsertVSETVLI] Relax tail policy more often for vmv.s.x
2023-05-31 18:18:44 +01:00
RISCVInstrFormats.td
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
RISCVInstrFormatsC.td
Recommit "[RISCV] Add .insn support for compressed formats."
2023-03-27 12:30:37 -07:00
RISCVInstrFormatsV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVInstrInfo.cpp
[SDAG] Preserve unpredictable metadata, teach X86CmovConversion to respect this metadata
2023-06-01 20:56:44 +02:00
RISCVInstrInfo.h
[RISCV] Custom lowering of llvm.is.fpclass
2023-04-26 10:17:18 +08:00
RISCVInstrInfo.td
[RISCV] Change LdPat and StPat from multiclass to class. NFC
2023-05-31 12:00:54 -07:00
RISCVInstrInfoA.td
[RISCV] Change LdPat and StPat from multiclass to class. NFC
2023-05-31 12:00:54 -07:00
RISCVInstrInfoC.td
[RISCV] Remove is*Branch instruction flags from C_JR
2023-04-11 09:28:18 +02:00
RISCVInstrInfoD.td
[RISCV] Change LdPat and StPat from multiclass to class. NFC
2023-05-31 12:00:54 -07:00
RISCVInstrInfoF.td
[RISCV] Change LdPat and StPat from multiclass to class. NFC
2023-05-31 12:00:54 -07:00
RISCVInstrInfoM.td
…
RISCVInstrInfoV.td
[RISCV] Switch vwsll.v* instructions to use the VSHT_IV_V_X_I class instead of VALU_IV_V_X_I.
2023-06-05 09:24:50 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Separate slideup/down pseudoinstructions from FMA instructions earlier in the class hierarchy.
2023-06-01 15:25:40 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Refactor predicates for rvv SDNode patterns.
2023-05-18 09:56:30 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add RISCVISD nodes for vfwadd/vfwsub.
2023-06-05 14:12:47 -07:00
RISCVInstrInfoXSf.td
[RISCV] Support LLVM IR intrinsics for xsfvcp extension.
2023-04-24 03:10:13 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Expand rotate by non-constant for XTHeadBb during lowering.
2023-05-23 16:31:22 -07:00
RISCVInstrInfoXVentana.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoZb.td
[RISCV] Ues PatGpr to reduce some tablegen code. NFC
2023-05-07 15:00:45 -07:00
RISCVInstrInfoZc.td
[RISCV] Add MC support of RISCV zcmp Extension
2023-05-08 14:29:50 +08:00
RISCVInstrInfoZfa.td
[RISCV] Rename WriteFCvtF32ToF32 sched class to WriteFRoundF32.
2023-04-24 12:02:53 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV][MC] Add support for experimental Zfbfmin extension
2023-05-19 15:17:56 +01:00
RISCVInstrInfoZfh.td
[RISCV] Change LdPat and StPat from multiclass to class. NFC
2023-05-31 12:00:54 -07:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZicond.td
[RISCV] Add codegen for the experimental zicond extension
2023-03-30 21:05:22 +01:00
RISCVInstrInfoZk.td
…
RISCVInstrInfoZvfbf.td
[RISCV][MC] Add support for experimental Zvfbfwma extension
2023-05-19 15:37:26 +01:00
RISCVInstrInfoZvk.td
[RISCV] Switch vwsll.v* instructions to use the VSHT_IV_V_X_I class instead of VALU_IV_V_X_I.
2023-06-05 09:24:50 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).
2023-06-06 11:59:12 -07:00
RISCVISelDAGToDAG.h
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
RISCVISelLowering.cpp
[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).
2023-06-06 11:59:12 -07:00
RISCVISelLowering.h
[RISCV] Lower experimental_get_vector_length intrinsic to vsetvli for some cases.
2023-06-05 15:02:11 -07:00
RISCVMachineFunctionInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMakeCompressible.cpp
[RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt
2023-05-16 09:10:49 +01:00
RISCVMCInstLower.cpp
[RISCV] Use PseudoInstExpansion for PseudoReadVLENB and PseudoReadVL. NFC
2023-04-06 09:33:01 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVOptWInstrs.cpp
[RISCV] Move allWUsers from RISCVInstrInfo to RISCVOptWInstrs.
2023-03-29 15:13:09 -07:00
RISCVProcessors.td
[RISCV] Add sifive-x280 processor with all of its extensions
2023-05-05 10:02:28 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.td
[NFC][RISCV] Replace global def containing only one field with defvar
2023-05-22 10:47:32 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVSchedRocket.td
[RISCV] Add MC support of RISCV zcmt Extension
2023-05-03 22:06:37 +08:00
RISCVSchedSiFive7.td
[RISCV][NFC] Add isF argument to SchedSEWSet
2023-06-01 12:44:49 +08:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add scheduling for Zfa instructions
2023-04-20 13:46:34 +08:00
RISCVSchedule.td
[RISCV] Rename WriteFCvtF32ToF32 sched class to WriteFRoundF32.
2023-04-24 12:02:53 -07:00
RISCVScheduleV.td
[RISCV][NFC] Add isF argument to SchedSEWSet
2023-06-01 12:44:49 +08:00
RISCVScheduleZb.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVSubtarget.cpp
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
2023-06-02 23:14:17 -07:00
RISCVSubtarget.h
[RISCV] Generalise shouldExtendTypeInLibcall logic to apply to all <XLEN floats on soft ABIs
2023-05-30 11:04:03 +01:00
RISCVSystemOperands.td
[RISCV] Add MC support of RISCV zcmt Extension
2023-05-03 22:06:37 +08:00
RISCVTargetMachine.cpp
[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.
2023-05-01 12:05:18 -07:00
RISCVTargetMachine.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.cpp
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetObjectFile.h
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetTransformInfo.cpp
[SLP][RISCV] Account for offset folding in getPointersChainCost
2023-05-22 13:55:30 +01:00
RISCVTargetTransformInfo.h
[SLP][RISCV] Account for offset folding in getPointersChainCost
2023-05-22 13:55:30 +01:00