d19218e507
When we have a floating-point operation that a target doesn't support for a given type, but does support for a wider type, then there are two ways this can be handled: * If the target doesn't have any registers at all of this type then LegalizeTypes will convert the operation. * If we do have registers but no operation for this type, then the operation action will be Promote and it's handled in PromoteNode. In both cases the operation at the wider type, and the conversion operations to and from that type, should have the same fast math flags as the original operation. This is being done in preparation for a DAGCombine patch which makes use of these fast math flags.
113 lines
5.9 KiB
LLVM
113 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=arm -mattr=+vfp4d16sp,-fullfp16 -stop-after=finalize-isel | FileCheck %s --check-prefixes=CHECK-CVT
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; RUN: llc < %s -mtriple=arm -mattr=+vfp4d16sp,+fullfp16 -stop-after=finalize-isel | FileCheck %s --check-prefixes=CHECK-FP16
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; Check that the output instructions have the same fast math flags as the input
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; fadd, even when f16 is legalized to f32.
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; FIXME: We don't get fast math flags on VCVTBHS because they get lost during a
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; DAGCombine transformation.
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; FIXME: We don't get fast math flags on VCVTBSH because the outermost node in
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; the isel pattern is COPY_TO_REGCLASS and the fast math flags end up there.
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define half @normal_fadd(half %x, half %y) {
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; CHECK-CVT-LABEL: name: normal_fadd
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; CHECK-CVT: bb.0.entry:
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; CHECK-CVT-NEXT: liveins: $r0, $r1
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; CHECK-CVT-NEXT: {{ $}}
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; CHECK-CVT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r1
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; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0
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; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]]
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; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]]
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; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
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; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
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; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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;
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; CHECK-FP16-LABEL: name: normal_fadd
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; CHECK-FP16: bb.0.entry:
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; CHECK-FP16-NEXT: liveins: $r0, $r1
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; CHECK-FP16-NEXT: {{ $}}
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; CHECK-FP16-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r1
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; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg
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; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]]
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; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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entry:
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%add = fadd half %x, %y
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ret half %add
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}
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define half @fast_fadd(half %x, half %y) {
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; CHECK-CVT-LABEL: name: fast_fadd
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; CHECK-CVT: bb.0.entry:
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; CHECK-CVT-NEXT: liveins: $r0, $r1
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; CHECK-CVT-NEXT: {{ $}}
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; CHECK-CVT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r1
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; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0
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; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]]
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; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]]
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; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
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; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
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; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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;
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; CHECK-FP16-LABEL: name: fast_fadd
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; CHECK-FP16: bb.0.entry:
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; CHECK-FP16-NEXT: liveins: $r0, $r1
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; CHECK-FP16-NEXT: {{ $}}
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; CHECK-FP16-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r1
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; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf nsz arcp contract afn reassoc VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg
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; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]]
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; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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entry:
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%add = fadd fast half %x, %y
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ret half %add
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}
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define half @ninf_fadd(half %x, half %y) {
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; CHECK-CVT-LABEL: name: ninf_fadd
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; CHECK-CVT: bb.0.entry:
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; CHECK-CVT-NEXT: liveins: $r0, $r1
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; CHECK-CVT-NEXT: {{ $}}
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; CHECK-CVT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r1
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; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0
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; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]]
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; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]]
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; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
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; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
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; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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;
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; CHECK-FP16-LABEL: name: ninf_fadd
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; CHECK-FP16: bb.0.entry:
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; CHECK-FP16-NEXT: liveins: $r0, $r1
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; CHECK-FP16-NEXT: {{ $}}
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; CHECK-FP16-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r1
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; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg
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; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]]
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; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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entry:
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%add = fadd ninf half %x, %y
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ret half %add
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}
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