8728c5f2db
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. llvm-svn: 310258
111 lines
2.8 KiB
LLVM
111 lines
2.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}br_cc_f16:
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_cmp_nlt_f32_e32 vcc, v[[B_F32]], v[[A_F32]]
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; VI: v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
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; GCN: s_cbranch_vccnz
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; GCN: one{{$}}
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; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[B_F32]]
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; GCN: buffer_store_short
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; GCN: s_endpgm
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; GCN: two{{$}}
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; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[A_F32]]
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; GCN: buffer_store_short v[[B_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @br_cc_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%b.val = load half, half addrspace(1)* %b
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%fcmp = fcmp olt half %a.val, %b.val
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br i1 %fcmp, label %one, label %two
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one:
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store half %a.val, half addrspace(1)* %r
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ret void
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two:
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store half %b.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}br_cc_f16_imm_a:
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_cmp_nlt_f32_e32 vcc, 0.5, v[[B_F32]]
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; SI: s_cbranch_vccnz
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; VI: v_cmp_nlt_f16_e32 vcc, 0.5, v[[B_F16]]
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; VI: s_cbranch_vccnz
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; GCN: one{{$}}
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; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x380{{0|1}}{{$}}
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; SI: buffer_store_short v[[A_F16]]
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; SI: s_endpgm
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; GCN: two{{$}}
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; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]]
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define amdgpu_kernel void @br_cc_f16_imm_a(
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half addrspace(1)* %r,
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half addrspace(1)* %b) {
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entry:
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%b.val = load half, half addrspace(1)* %b
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%fcmp = fcmp olt half 0xH3800, %b.val
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br i1 %fcmp, label %one, label %two
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one:
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store half 0xH3800, half addrspace(1)* %r
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ret void
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two:
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store half %b.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}br_cc_f16_imm_b:
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_cmp_ngt_f32_e32 vcc, 0.5, v[[A_F32]]
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; VI: v_cmp_ngt_f16_e32 vcc, 0.5, v[[A_F16]]
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; GCN: s_cbranch_vccnz
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; GCN: one{{$}}
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; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]]
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; GCN: two{{$}}
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; VI: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x3800{{$}}
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; GCN: buffer_store_short v[[B_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @br_cc_f16_imm_b(
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half addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%fcmp = fcmp olt half %a.val, 0xH3800
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br i1 %fcmp, label %one, label %two
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one:
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store half %a.val, half addrspace(1)* %r
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ret void
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two:
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store half 0xH3800, half addrspace(1)* %r
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ret void
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}
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