da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
219 lines
8.3 KiB
LLVM
219 lines
8.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
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; Make sure we don't try to form FMAX_LEGACY nodes with f64
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define amdgpu_kernel void @test_fmax_legacy_uge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
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; SI-LABEL: test_fmax_legacy_uge_f64:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s10, 0
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
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; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_fmax_legacy_uge_f64:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
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; VI-NEXT: v_mov_b32_e32 v4, s0
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; VI-NEXT: v_mov_b32_e32 v5, s1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]
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; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
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; VI-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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%a = load double, double addrspace(1)* %gep.0, align 8
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%b = load double, double addrspace(1)* %gep.1, align 8
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%cmp = fcmp uge double %a, %b
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%val = select i1 %cmp, double %a, double %b
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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define amdgpu_kernel void @test_fmax_legacy_oge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
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; SI-LABEL: test_fmax_legacy_oge_f64:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s10, 0
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]
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; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_fmax_legacy_oge_f64:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
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; VI-NEXT: v_mov_b32_e32 v4, s0
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; VI-NEXT: v_mov_b32_e32 v5, s1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]
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; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
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; VI-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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%a = load double, double addrspace(1)* %gep.0, align 8
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%b = load double, double addrspace(1)* %gep.1, align 8
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%cmp = fcmp oge double %a, %b
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%val = select i1 %cmp, double %a, double %b
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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define amdgpu_kernel void @test_fmax_legacy_ugt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
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; SI-LABEL: test_fmax_legacy_ugt_f64:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s10, 0
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]
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; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_fmax_legacy_ugt_f64:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
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; VI-NEXT: v_mov_b32_e32 v4, s0
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; VI-NEXT: v_mov_b32_e32 v5, s1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]
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; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
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; VI-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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%a = load double, double addrspace(1)* %gep.0, align 8
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%b = load double, double addrspace(1)* %gep.1, align 8
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%cmp = fcmp ugt double %a, %b
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%val = select i1 %cmp, double %a, double %b
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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define amdgpu_kernel void @test_fmax_legacy_ogt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
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; SI-LABEL: test_fmax_legacy_ogt_f64:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s10, 0
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]
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; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_fmax_legacy_ogt_f64:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
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; VI-NEXT: v_mov_b32_e32 v4, s0
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; VI-NEXT: v_mov_b32_e32 v5, s1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]
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; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
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; VI-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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%a = load double, double addrspace(1)* %gep.0, align 8
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%b = load double, double addrspace(1)* %gep.1, align 8
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%cmp = fcmp ogt double %a, %b
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%val = select i1 %cmp, double %a, double %b
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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