da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
158 lines
5.1 KiB
LLVM
158 lines
5.1 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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declare half @llvm.fabs.f16(half %a)
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declare i1 @llvm.amdgcn.class.f16(half %a, i32 %b)
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; GCN-LABEL: {{^}}class_f16:
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; GCN-DAG: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN-DAG: buffer_load_dword v[[B_I32:[0-9]+]]
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; VI: v_cmp_class_f16_e32 vcc, v[[A_F16]], v[[B_I32]]
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; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]]
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; GCN: buffer_store_dword v[[R_I32]]
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; GCN: s_endpgm
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define amdgpu_kernel void @class_f16(
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i32 addrspace(1)* %r,
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half addrspace(1)* %a,
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i32 addrspace(1)* %b) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%b.val = load i32, i32 addrspace(1)* %b
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%r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 %b.val)
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%r.val.sext = sext i1 %r.val to i32
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store i32 %r.val.sext, i32 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}class_f16_fabs:
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; GCN: s_load_dword s[[SB_I32:[0-9]+]]
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; GCN: s_load_dword s[[SA_F16:[0-9]+]]
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; GCN: v_mov_b32_e32 [[V_B_I32:v[0-9]+]], s[[SB_I32]]
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; VI: v_cmp_class_f16_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], |s[[SA_F16]]|, [[V_B_I32]]
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; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
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; GCN: buffer_store_dword v[[VR_I32]]
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; GCN: s_endpgm
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define amdgpu_kernel void @class_f16_fabs(
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i32 addrspace(1)* %r,
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[8 x i32],
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half %a.val,
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[8 x i32],
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i32 %b.val) {
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entry:
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%a.val.fabs = call half @llvm.fabs.f16(half %a.val)
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%r.val = call i1 @llvm.amdgcn.class.f16(half %a.val.fabs, i32 %b.val)
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%r.val.sext = sext i1 %r.val to i32
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store i32 %r.val.sext, i32 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}class_f16_fneg:
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; GCN: s_load_dword s[[SB_I32:[0-9]+]]
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; GCN: s_load_dword s[[SA_F16:[0-9]+]]
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; GCN: v_mov_b32_e32 [[V_B_I32:v[0-9]+]], s[[SB_I32]]
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; VI: v_cmp_class_f16_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -s[[SA_F16]], [[V_B_I32]]
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; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
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; GCN: buffer_store_dword v[[VR_I32]]
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; GCN: s_endpgm
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define amdgpu_kernel void @class_f16_fneg(
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i32 addrspace(1)* %r,
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[8 x i32],
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half %a.val,
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[8 x i32],
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i32 %b.val) {
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entry:
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%a.val.fneg = fsub half -0.0, %a.val
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%r.val = call i1 @llvm.amdgcn.class.f16(half %a.val.fneg, i32 %b.val)
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%r.val.sext = sext i1 %r.val to i32
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store i32 %r.val.sext, i32 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}class_f16_fabs_fneg:
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; GCN: s_load_dword s[[SB_I32:[0-9]+]]
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; GCN: s_load_dword s[[SA_F16:[0-9]+]]
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; GCN: v_mov_b32_e32 [[V_B_I32:v[0-9]+]], s[[SB_I32]]
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; VI: v_cmp_class_f16_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -|s[[SA_F16]]|, [[V_B_I32]]
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; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
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; GCN: buffer_store_dword v[[VR_I32]]
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; GCN: s_endpgm
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define amdgpu_kernel void @class_f16_fabs_fneg(
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i32 addrspace(1)* %r,
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[8 x i32],
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half %a.val,
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[8 x i32],
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i32 %b.val) {
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entry:
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%a.val.fabs = call half @llvm.fabs.f16(half %a.val)
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%a.val.fabs.fneg = fsub half -0.0, %a.val.fabs
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%r.val = call i1 @llvm.amdgcn.class.f16(half %a.val.fabs.fneg, i32 %b.val)
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%r.val.sext = sext i1 %r.val to i32
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store i32 %r.val.sext, i32 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}class_f16_1:
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; GCN: s_load_dword s[[SA_F16:[0-9]+]]
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; VI: v_cmp_class_f16_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s[[SA_F16]], 1{{$}}
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; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
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; GCN: buffer_store_dword v[[VR_I32]]
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; GCN: s_endpgm
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define amdgpu_kernel void @class_f16_1(
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i32 addrspace(1)* %r,
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half %a.val) {
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entry:
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%r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 1)
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%r.val.sext = sext i1 %r.val to i32
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store i32 %r.val.sext, i32 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}class_f16_64
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; GCN: s_load_dword s[[SA_F16:[0-9]+]]
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; VI: v_cmp_class_f16_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s[[SA_F16]], 64{{$}}
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; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
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; GCN: buffer_store_dword v[[VR_I32]]
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; GCN: s_endpgm
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define amdgpu_kernel void @class_f16_64(
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i32 addrspace(1)* %r,
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half %a.val) {
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entry:
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%r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 64)
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%r.val.sext = sext i1 %r.val to i32
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store i32 %r.val.sext, i32 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}class_f16_full_mask:
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; GCN: s_load_dword s[[SA_F16:[0-9]+]]
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; VI: v_mov_b32_e32 v[[MASK:[0-9]+]], 0x3ff{{$}}
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; VI: v_cmp_class_f16_e32 vcc, s[[SA_F16]], v[[MASK]]
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; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, vcc
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; GCN: buffer_store_dword v[[VR_I32]]
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; GCN: s_endpgm
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define amdgpu_kernel void @class_f16_full_mask(
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i32 addrspace(1)* %r,
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half %a.val) {
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entry:
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%r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 1023)
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%r.val.sext = sext i1 %r.val to i32
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store i32 %r.val.sext, i32 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}class_f16_nine_bit_mask:
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; GCN: s_load_dword s[[SA_F16:[0-9]+]]
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; VI: v_mov_b32_e32 v[[MASK:[0-9]+]], 0x1ff{{$}}
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; VI: v_cmp_class_f16_e32 vcc, s[[SA_F16]], v[[MASK]]
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; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, vcc
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; GCN: buffer_store_dword v[[VR_I32]]
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; GCN: s_endpgm
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define amdgpu_kernel void @class_f16_nine_bit_mask(
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i32 addrspace(1)* %r,
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half %a.val) {
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entry:
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%r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 511)
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%r.val.sext = sext i1 %r.val to i32
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store i32 %r.val.sext, i32 addrspace(1)* %r
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ret void
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}
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