0f20a35b9e
Summary: In general, we need queue_ptr for aperture bases and trap handling, and user SGPRs have to be set up to hold queue_ptr. In current implementation, user SGPRs are set up unnecessarily for some cases. If the target has aperture registers, queue_ptr is not needed to reference aperture bases. For trap handling, if target suppots getDoorbellID, queue_ptr is also not necessary. Futher, code object version 5 introduces new kernel ABI which passes queue_ptr as an implicit kernel argument, so user SGPRs are no longer necessary for queue_ptr. Based on the trap handling document: https://llvm.org/docs/AMDGPUUsage.html#amdgpu-trap-handler-for-amdhsa-os-v4-onwards-table, llvm.debugtrap does not need queue_ptr, we remove queue_ptr suport for llvm.debugtrap in the backend. Reviewers: sameerds, arsenm Fixes: SWDEV-307189 Differential Revision: https://reviews.llvm.org/D119762
51 lines
1.9 KiB
LLVM
51 lines
1.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; GCN-LABEL: {{^}}is_local_vgpr:
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; GCN-DAG: {{flat|global}}_load_dwordx2 v{{\[[0-9]+}}:[[PTR_HI:[0-9]+]]]
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; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10
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; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
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; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16
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; GCN: v_cmp_eq_u32_e32 vcc, [[APERTURE]], v[[PTR_HI]]
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id
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%ptr = load volatile i8*, i8* addrspace(1)* %gep
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%val = call i1 @llvm.amdgcn.is.shared(i8* %ptr)
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%ext = zext i1 %val to i32
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store i32 %ext, i32 addrspace(1)* undef
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ret void
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}
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; FIXME: setcc (zero_extend (setcc)), 1) not folded out, resulting in
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; select and vcc branch.
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; GCN-LABEL: {{^}}is_local_sgpr:
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; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}}
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; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
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; GFX9-DAG: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16
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; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x1{{$}}
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; GFX9-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[4:5], 0x4{{$}}
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; GCN: s_cmp_eq_u32 [[PTR_HI]], [[APERTURE]]
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @is_local_sgpr(i8* %ptr) {
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%val = call i1 @llvm.amdgcn.is.shared(i8* %ptr)
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br i1 %val, label %bb0, label %bb1
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bb0:
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store volatile i32 0, i32 addrspace(1)* undef
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br label %bb1
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bb1:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #0
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attributes #0 = { nounwind readnone speculatable }
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