3a20597776
Implement an intrinsic for use lowering LDS variables to different addresses from different kernels. This will allow kernels that cannot reach an LDS variable to avoid wasting space for it. There are a number of implicit arguments accessed by intrinsic already so this implementation closely follows the existing handling. It is slightly novel in that this SGPR is written by the kernel prologue. It is necessary in the general case to put variables at different addresses such that they can be compactly allocated and thus necessary for an indirect function call to have some means of determining where a given variable was allocated. Claiming an arbitrary SGPR into which an integer can be written by the kernel, in this implementation based on metadata associated with that kernel, which is then passed on to indirect call sites is sufficient to determine the variable address. The intent is to emit a __const array of LDS addresses and index into it. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D125060
83 lines
2.8 KiB
LLVM
83 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.amdgcn.lds.kernel.id()
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declare i32 @llvm.amdgcn.workgroup.id.x()
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define void @function_lds_id(i32 addrspace(1)* %out) {
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; GCN-LABEL: function_lds_id:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_add_i32 s4, s15, s12
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; GCN-NEXT: v_mov_b32_e32 v2, s4
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; GCN-NEXT: flat_store_dword v[0:1], v2
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%tmp0 = call i32 @llvm.amdgcn.lds.kernel.id()
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%help = call i32 @llvm.amdgcn.workgroup.id.x()
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%both = add i32 %tmp0, %help
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store i32 %both, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @kernel_lds_id(i32 addrspace(1)* %out) !llvm.amdgcn.lds.kernel.id !0 {
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; GCN-LABEL: kernel_lds_id:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GCN-NEXT: s_add_i32 s2, s6, 42
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; GCN-NEXT: v_mov_b32_e32 v2, s2
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: flat_store_dword v[0:1], v2
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; GCN-NEXT: s_endpgm
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%tmp0 = call i32 @llvm.amdgcn.lds.kernel.id()
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%help = call i32 @llvm.amdgcn.workgroup.id.x()
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%both = add i32 %tmp0, %help
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store i32 %both, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @indirect_lds_id(i32 addrspace(1)* %out) !llvm.amdgcn.lds.kernel.id !1 {
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; GCN-LABEL: indirect_lds_id:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_mov_b32 s32, 0
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; GCN-NEXT: s_mov_b32 flat_scratch_lo, s7
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; GCN-NEXT: s_add_i32 s6, s6, s9
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; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s6, 8
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; GCN-NEXT: s_add_u32 s0, s0, s9
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; GCN-NEXT: s_getpc_b64 s[6:7]
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; GCN-NEXT: s_add_u32 s6, s6, function_lds_id@gotpcrel32@lo+4
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; GCN-NEXT: s_addc_u32 s7, s7, function_lds_id@gotpcrel32@hi+12
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; GCN-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
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; GCN-NEXT: s_mov_b32 s15, 21
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; GCN-NEXT: s_mov_b32 s12, s8
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: s_swappc_b64 s[30:31], s[6:7]
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; GCN-NEXT: s_endpgm
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call void @function_lds_id(i32 addrspace(1) * %out)
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ret void
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}
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define amdgpu_kernel void @doesnt_use_it(i32 addrspace(1)* %out) !llvm.amdgcn.lds.kernel.id !0 {
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; GCN-LABEL: doesnt_use_it:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GCN-NEXT: v_mov_b32_e32 v2, 0x64
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: flat_store_dword v[0:1], v2
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; GCN-NEXT: s_endpgm
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store i32 100, i32 addrspace(1)* %out
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ret void
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}
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!0 = !{i32 42}
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!1 = !{i32 21}
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