Jeff Niu b2ccfb4d95 [mlir][LLVMIR] Change ShuffleVectorOp to use assembly format ...

This patch moves `LLVM::ShuffleVectorOp` to assembly format and in the
process drops the extra type that can be inferred (both operand types
are required to be the same) and switches to a dense integer array.

The syntax change:

```
// Before
%0 = llvm.shufflevector %0, %1 [0 : i32, 0 : i32, 0 : i32, 0 : i32] : vector<4xf32>, vector<4xf32>
// After
%0 = llvm.shufflevector %0, %1 [0, 0, 0, 0] : vector<4xf32>
```

Reviewed By: dcaballe

Differential Revision: https://reviews.llvm.org/D132038

2022-08-18 12:46:04 -04:00

..

AffineToStandard

[mlir] Flip more uses to prefixed accessor form (NFC).

2022-06-26 19:12:38 -07:00

AMDGPUToROCDL

[mlir][LLVMIR] (NFC) Add convenience builders for ConstantOp

2022-08-09 15:34:36 -04:00

ArithmeticToLLVM

[MLIR][NFC] Sort table of operations alphabetically

2022-08-18 10:31:27 +01:00

ArithmeticToSPIRV

[mlir][spirv] Add arith.addi_carry to spv.IAddCarry conversion

2022-08-17 21:33:34 -04:00

ArmNeon2dToIntr

[mlir] Update accessors to prefixed form (NFC)

2022-06-18 17:53:22 -07:00

AsyncToLLVM

[mlir][LLVMIR] Clean up the definitions of ReturnOp/CallOp

2022-08-11 00:35:02 -04:00

BufferizationToMemRef

[mlir] (NFC) run clang-format on all files

2022-07-14 13:32:13 -07:00

ComplexToLibm

[mlir][complex] Mark all supported operation illegal explicitly for complex to libm

2022-08-15 17:02:16 -04:00

ComplexToLLVM

[mlir] (NFC) Clean up bazel and CMake target names

2022-06-13 16:24:15 +00:00

ComplexToStandard

Don't lower log1p(x) to log(1 + x).

2022-08-16 06:58:00 +02:00

ControlFlowToLLVM

[mlir] Only conditionally lower CF branching ops to LLVM

2022-08-04 16:36:27 +02:00

ControlFlowToSPIRV

[mlir][spirv] Turn various passes to plain OperationPass

2022-08-10 13:50:07 -04:00

FuncToLLVM

[mlir][LLVMIR] Clean up the definitions of ReturnOp/CallOp

2022-08-11 00:35:02 -04:00

FuncToSPIRV

[mlir][spirv] Turn various passes to plain OperationPass

2022-08-10 13:50:07 -04:00

GPUCommon

[mlir][LLVMIR] Clean up the definitions of ReturnOp/CallOp

2022-08-11 00:35:02 -04:00

GPUToNVVM

[mlir][LLVMIR] "Modernize" Insert/ExtractValueOp

2022-08-10 12:51:11 -04:00

GPUToROCDL

[mlir][math] Rename math.abs -> math.absf

2022-08-08 11:04:58 -04:00

GPUToSPIRV

[mlir][spirv] Turn various passes to plain OperationPass

2022-08-10 13:50:07 -04:00

GPUToVulkan

[mlir][LLVMIR] Clean up the definitions of ReturnOp/CallOp

2022-08-11 00:35:02 -04:00

LinalgToLLVM

[mlir] move SCF headers to SCF/{IR,Transforms} respectively

2022-06-20 10:18:01 +02:00

LinalgToSPIRV

[mlir] Flip LinAlg dialect to _Both

2022-07-19 14:42:58 -07:00

LinalgToStandard

[mlir] (NFC) run clang-format on all files

2022-07-14 13:32:13 -07:00

LLVMCommon

[mlir][LLVMIR] Clean up the definitions of ReturnOp/CallOp

2022-08-11 00:35:02 -04:00

MathToLibm

Don't lower log1p(x) to log(1 + x).

2022-08-16 06:58:00 +02:00

MathToLLVM

[mlir][math] Fix lowering of AbsIOp

2022-08-12 12:10:15 -04:00

MathToSPIRV

[mlir][spirv] Turn various passes to plain OperationPass

2022-08-10 13:50:07 -04:00

MemRefToLLVM

[mlir][LLVMIR] Clean up the definitions of ReturnOp/CallOp

2022-08-11 00:35:02 -04:00

MemRefToSPIRV

[mlir][spirv] Turn various passes to plain OperationPass

2022-08-10 13:50:07 -04:00

NVGPUToNVVM

[mlir][LLVMIR] "Modernize" Insert/ExtractValueOp

2022-08-10 12:51:11 -04:00

OpenACCToLLVM

[mlir] (NFC) Clean up bazel and CMake target names

2022-06-13 16:24:15 +00:00

OpenACCToSCF

[mlir] move SCF headers to SCF/{IR,Transforms} respectively

2022-06-20 10:18:01 +02:00

OpenMPToLLVM

[Flang][OpenMP] Fix conversion of nested loops for SIMD directive

2022-08-10 03:54:30 -05:00

PDLToPDLInterp

[mlir] (NFC) Clean up bazel and CMake target names

2022-06-13 16:24:15 +00:00

ReconcileUnrealizedCasts

[MLIR] Reconciliation of chains of unrealized casts

2022-08-03 11:57:20 +00:00

SCFToControlFlow

[mlir] Use C++17 structured bindings instead of std::tie where applicable. NFCI

2022-08-09 13:34:17 +02:00

SCFToGPU

[mlir] move SCF headers to SCF/{IR,Transforms} respectively

2022-06-20 10:18:01 +02:00

SCFToOpenMP

[mlir] move SCF headers to SCF/{IR,Transforms} respectively

2022-06-20 10:18:01 +02:00

SCFToSPIRV

[mlir][spirv] Turn various passes to plain OperationPass

2022-08-10 13:50:07 -04:00

ShapeToStandard

[mlir][shape] Rename dim.dim to dim.index (NFC)

2022-08-13 09:34:37 -07:00

SPIRVCommon

[mlir][spirv] Allow converting from index type in unsigned ops

2022-04-27 10:13:50 -04:00

SPIRVToLLVM

[mlir][LLVMIR] Change ShuffleVectorOp to use assembly format

2022-08-18 12:46:04 -04:00

TensorToLinalg

[mlir] (NFC) Clean up bazel and CMake target names

2022-06-13 16:24:15 +00:00

TensorToSPIRV

[mlir][spirv] Turn various passes to plain OperationPass

2022-08-10 13:50:07 -04:00

TosaToArith

[mlir][tosa] Flip accessors used to prefixed form (NFC)

2022-07-22 09:56:08 -07:00

TosaToLinalg

[MLIR][TOSA] Remove ReluN operator from TOSA dialect

2022-08-12 16:00:11 -07:00

TosaToSCF

[mlir][tosa] Flip accessors used to prefixed form (NFC)

2022-07-22 09:56:08 -07:00

TosaToTensor

[mlir][tosa] Flip accessors used to prefixed form (NFC)

2022-07-22 09:56:08 -07:00

VectorToGPU

[mlir][NVGPU] nvgpu.mmasync on F32 through TF32

2022-08-01 23:23:27 +00:00

VectorToLLVM

[mlir][LLVMIR] Change ShuffleVectorOp to use assembly format

2022-08-18 12:46:04 -04:00

VectorToSCF

Convert for_each to range-based for loops (NFC)

2022-07-23 12:17:27 -07:00

VectorToSPIRV

[mlir][spirv] Turn various passes to plain OperationPass

2022-08-10 13:50:07 -04:00

CMakeLists.txt

[mlir] Remove VectorToROCDL

2022-07-12 15:21:22 +00:00

PassDetail.h

[MLIR][GPU] Add NvGpu mma.sync path to the VectorToGPU pass

2022-05-20 09:42:55 -06:00