85aff8a4e4
Summary: The RISC-V debug register was named dscratch in a previous draft of the RISC-V debug mode spec. The number of registers has been increased to 2 in the latest ratified version of the debug mode spec and the registers were named dscratch0 and dscratch1. We still support using the old register name "dscratch", but it would be disassembled as "dscratch0" with this change. Reviewers: apazos, asb, lenary, luismarques Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78764
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