5fb3a57ea7
LoopUnroll estimates the loop size via getInstructionCost(), but getInstructionCost() cannot pass CostKind to getVectorInstrCost(). And so does getShuffleCost() to getBroadcastShuffleOverhead(), getPermuteShuffleOverhead(), getExtractSubvectorOverhead(), and getInsertSubvectorOverhead(). To address this, this patch adds an argument CostKind to these functions. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D142116
72 lines
3.0 KiB
C++
72 lines
3.0 KiB
C++
//===- R600TargetTransformInfo.h - R600 specific TTI --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// R600 target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
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#include "AMDGPUTargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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namespace llvm {
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class R600Subtarget;
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class AMDGPUTargetLowering;
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class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
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using BaseT = BasicTTIImplBase<R600TTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const R600Subtarget *ST;
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const AMDGPUTargetLowering *TLI;
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AMDGPUTTIImpl CommonTTI;
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public:
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explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
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const R600Subtarget *getST() const { return ST; }
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const AMDGPUTargetLowering *getTLI() const { return TLI; }
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP,
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OptimizationRemarkEmitter *ORE);
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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unsigned getHardwareNumberOfRegisters(bool Vec) const;
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unsigned getNumberOfRegisters(bool Vec) const;
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TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
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unsigned getMinVectorRegisterBitWidth() const;
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unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
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bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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unsigned getMaxInterleaveFactor(unsigned VF);
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InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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using BaseT::getVectorInstrCost;
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InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
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TTI::TargetCostKind CostKind,
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unsigned Index, Value *Op0, Value *Op1);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
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