be3f4591af
This is used to help get simplified CFG for divergent regions as well as
get better code generation in some cases.
For example, with below IR:
```
define amdgpu_kernel void @test() {
bb:
br label %bb1
bb1:
%tmp = phi i32 [ 0, %bb ], [ %tmp5, %bb4 ]
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%cnd = icmp eq i32 %tid, 0
br i1 %cnd, label %bb4, label %bb2
bb2:
%tmp3 = add nsw i32 %tmp, 1
br label %bb4
bb4:
%tmp5 = phi i32 [ %tmp3, %bb2 ], [ %tmp, %bb1 ]
store volatile i32 %tmp5, ptr addrspace(1) undef
br label %bb1
}
```
We got below assembly before the change:
```
v_mov_b32_e32 v1, 0
v_cmp_eq_u32_e32 vcc, 0, v0
s_branch .LBB0_2
.LBB0_1: ; %bb4
; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s2, -1
s_mov_b32 s3, 0xf000
buffer_store_dword v1, off, s[0:3], 0
s_waitcnt vmcnt(0)
.LBB0_2: ; %bb
; =>This Inner Loop Header: Depth=1
s_and_saveexec_b64 s[0:1], vcc
s_xor_b64 s[0:1], exec, s[0:1]
; kill: def $sgpr0_sgpr1 killed $sgpr0_sgpr1 killed $exec
s_cbranch_execnz .LBB0_1
; %bb.3: ; %bb2
; in Loop: Header=BB0_2 Depth=1
s_or_b64 exec, exec, s[0:1]
s_waitcnt expcnt(0)
v_add_i32_e64 v1, s[0:1], 1, v1
s_branch .LBB0_1
```
After the change:
```
s_mov_b32 s0, 0
v_cmp_eq_u32_e32 vcc, 0, v0
s_mov_b32 s2, -1
s_mov_b32 s3, 0xf000
v_mov_b32_e32 v0, s0
s_branch .LBB0_2
.LBB0_1: ; %bb4
; in Loop: Header=BB0_2 Depth=1
buffer_store_dword v0, off, s[0:3], 0
s_waitcnt vmcnt(0)
.LBB0_2: ; %bb1
; =>This Inner Loop Header: Depth=1
s_and_saveexec_b64 s[0:1], vcc
s_cbranch_execnz .LBB0_1
; %bb.3: ; %bb2
; in Loop: Header=BB0_2 Depth=1
s_or_b64 exec, exec, s[0:1]
s_waitcnt expcnt(0)
v_add_i32_e64 v0, s[0:1], 1, v0
s_branch .LBB0_1
```
We are using one less VGPR, one less s_xor_, and better LICM with one
additional branch after the change. Please note the experiment
was done with reverting the workaround D139780, as it will stop the
tail-duplication completely for this case.
Reviewed by: arsenm
Differential Revision: https://reviews.llvm.org/D118250
60 lines
2.3 KiB
LLVM
60 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -amdgpu-atomic-optimizations < %s | FileCheck %s -check-prefixes=GFX10
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declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)
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declare i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32, <4 x i32>, i32, i32, i32 immarg)
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declare float @llvm.amdgcn.strict.wqm.f32(float)
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define amdgpu_ps void @main(i32 %arg) {
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; GFX10-LABEL: main:
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; GFX10: ; %bb.0: ; %bb
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; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: s_mov_b32 s1, exec_lo
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; GFX10-NEXT: s_mov_b32 s4, 0
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; GFX10-NEXT: s_mov_b32 s2, 0
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; GFX10-NEXT: s_branch .LBB0_2
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; GFX10-NEXT: .LBB0_1: ; %Flow
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; GFX10-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GFX10-NEXT: s_waitcnt_depctr 0xffe3
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s3
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; GFX10-NEXT: s_and_b32 s0, exec_lo, vcc_lo
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; GFX10-NEXT: s_or_b32 s2, s0, s2
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; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
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; GFX10-NEXT: s_cbranch_execz .LBB0_5
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; GFX10-NEXT: .LBB0_2: ; %bb4
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; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX10-NEXT: s_and_saveexec_b32 s3, s1
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; GFX10-NEXT: s_cbranch_execz .LBB0_1
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; GFX10-NEXT: ; %bb.3: ; in Loop: Header=BB0_2 Depth=1
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; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
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; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v1
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; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s0
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; GFX10-NEXT: s_cbranch_execz .LBB0_1
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; GFX10-NEXT: ; %bb.4: ; in Loop: Header=BB0_2 Depth=1
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; GFX10-NEXT: s_mov_b32 s5, s4
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; GFX10-NEXT: s_mov_b32 s6, s4
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; GFX10-NEXT: s_mov_b32 s7, s4
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; GFX10-NEXT: buffer_atomic_and v0, off, s[4:7], 0
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; GFX10-NEXT: s_branch .LBB0_1
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; GFX10-NEXT: .LBB0_5: ; %bb8
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
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; GFX10-NEXT: s_mov_b32 s0, 0
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-NEXT: exp mrt0 off, off, off, off
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; GFX10-NEXT: s_endpgm
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bb:
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br label %bb4
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bb4:
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%i5 = call i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32 0, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)
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%i7 = icmp eq i32 %arg, 1
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br i1 %i7, label %bb8, label %bb4
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bb8:
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%i9 = call float @llvm.amdgcn.strict.wqm.f32(float 0.0)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float %i9, float 0.0, float 0.0, float 0.0, i1 false, i1 false)
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ret void
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}
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