499abb243c
Remapping memory spaces is a function often needed in type conversions, most often when going to LLVM or to/from SPIR-V (a future commit), and it is possible that such remappings may become more common in the future as dialects take advantage of the more generic memory space infrastructure. Currently, memory space remappings are handled by running a special-purpose conversion pass before the main conversion that changes the address space attributes. In this commit, this approach is replaced by adding a notion of type attribute conversions TypeConverter, which is then used to convert memory space attributes. Then, we use this infrastructure throughout the *ToLLVM conversions. This has the advantage of loosing the requirements on the inputs to those passes from "all address spaces must be integers" to "all memory spaces must be convertible to integer spaces", a looser requirement that reduces the coupling between portions of MLIR. ON top of that, this change leads to the removal of most of the calls to getMemorySpaceAsInt(), bringing us closer to removing it. (A rework of the SPIR-V conversions to use this new system will be in a folowup commit.) As a note, one long-term motivation for this change is that I would eventually like to add an allocaMemorySpace key to MLIR data layouts and then call getMemRefAddressSpace(allocaMemorySpace) in the relevant *ToLLVM in order to ensure all alloca()s, whether incoming or produces during the LLVM lowering, have the correct address space for a given target. I expect that the type attribute conversion system may be useful in other contexts. Reviewed By: ftynse Differential Revision: https://reviews.llvm.org/D142159
293 lines
13 KiB
C++
293 lines
13 KiB
C++
//===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass to generate ROCDLIR operations for higher-level
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// GPU operations.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h"
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#include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h"
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#include "mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h"
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#include "mlir/Conversion/ArithToLLVM/ArithToLLVM.h"
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#include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h"
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#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
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#include "mlir/Conversion/LLVMCommon/LoweringOptions.h"
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#include "mlir/Conversion/LLVMCommon/Pattern.h"
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#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
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#include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h"
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#include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h"
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#include "mlir/Dialect/ControlFlow/IR/ControlFlow.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/GPU/Transforms/Passes.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/LLVMIR/ROCDLDialect.h"
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#include "mlir/Dialect/Math/IR/Math.h"
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#include "mlir/Dialect/Vector/IR/VectorOps.h"
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#include "mlir/IR/BuiltinAttributes.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "../GPUCommon/GPUOpsLowering.h"
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#include "../GPUCommon/IndexIntrinsicsOpLowering.h"
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#include "../GPUCommon/OpToFuncCallLowering.h"
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namespace mlir {
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#define GEN_PASS_DEF_CONVERTGPUOPSTOROCDLOPS
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#include "mlir/Conversion/Passes.h.inc"
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} // namespace mlir
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using namespace mlir;
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/// Returns true if the given `gpu.func` can be safely called using the bare
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/// pointer calling convention.
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static bool canBeCalledWithBarePointers(gpu::GPUFuncOp func) {
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bool canBeBare = true;
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for (Type type : func.getArgumentTypes())
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if (auto memrefTy = type.dyn_cast<BaseMemRefType>())
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canBeBare &= LLVMTypeConverter::canConvertToBarePtr(memrefTy);
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return canBeBare;
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}
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namespace {
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/// Import the GPU Ops to ROCDL Patterns.
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#include "GPUToROCDL.cpp.inc"
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// A pass that replaces all occurrences of GPU device operations with their
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// corresponding ROCDL equivalent.
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//
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// This pass only handles device code and is not meant to be run on GPU host
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// code.
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struct LowerGpuOpsToROCDLOpsPass
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: public impl::ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> {
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LowerGpuOpsToROCDLOpsPass() = default;
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LowerGpuOpsToROCDLOpsPass(const std::string &chipset, unsigned indexBitwidth,
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bool useBarePtrCallConv,
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gpu::amd::Runtime runtime) {
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if (this->chipset.getNumOccurrences() == 0)
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this->chipset = chipset;
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if (this->indexBitwidth.getNumOccurrences() == 0)
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this->indexBitwidth = indexBitwidth;
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if (this->useBarePtrCallConv.getNumOccurrences() == 0)
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this->useBarePtrCallConv = useBarePtrCallConv;
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if (this->runtime.getNumOccurrences() == 0)
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this->runtime = runtime;
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}
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void runOnOperation() override {
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gpu::GPUModuleOp m = getOperation();
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MLIRContext *ctx = m.getContext();
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// Request C wrapper emission.
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for (auto func : m.getOps<func::FuncOp>()) {
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func->setAttr(LLVM::LLVMDialect::getEmitCWrapperAttrName(),
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UnitAttr::get(ctx));
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}
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FailureOr<amdgpu::Chipset> maybeChipset = amdgpu::Chipset::parse(chipset);
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if (failed(maybeChipset)) {
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emitError(UnknownLoc::get(ctx), "Invalid chipset name: " + chipset);
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return signalPassFailure();
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}
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/// Customize the bitwidth used for the device side index computations.
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LowerToLLVMOptions options(
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ctx, DataLayout(cast<DataLayoutOpInterface>(m.getOperation())));
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if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout)
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options.overrideIndexBitwidth(indexBitwidth);
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if (useBarePtrCallConv) {
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options.useBarePtrCallConv = true;
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WalkResult canUseBarePointers =
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m.walk([](gpu::GPUFuncOp func) -> WalkResult {
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if (canBeCalledWithBarePointers(func))
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return WalkResult::advance();
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return WalkResult::interrupt();
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});
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if (canUseBarePointers.wasInterrupted()) {
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emitError(UnknownLoc::get(ctx),
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"bare pointer calling convention requires all memrefs to "
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"have static shape and use the identity map");
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return signalPassFailure();
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}
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}
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// Apply in-dialect lowering. In-dialect lowering will replace
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// ops which need to be lowered further, which is not supported by a
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// single conversion pass.
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{
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RewritePatternSet patterns(ctx);
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populateGpuRewritePatterns(patterns);
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(void)applyPatternsAndFoldGreedily(m, std::move(patterns));
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}
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LLVMTypeConverter converter(ctx, options);
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populateGpuMemorySpaceAttributeConversions(
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converter, [](gpu::AddressSpace space) {
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switch (space) {
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case gpu::AddressSpace::Global:
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return 1;
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case gpu::AddressSpace::Workgroup:
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return 3;
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case gpu::AddressSpace::Private:
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return 5;
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}
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llvm_unreachable("unknown address space enum value");
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return 0;
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});
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RewritePatternSet llvmPatterns(ctx);
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mlir::arith::populateArithToLLVMConversionPatterns(converter, llvmPatterns);
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populateAMDGPUToROCDLConversionPatterns(converter, llvmPatterns,
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*maybeChipset);
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populateVectorToLLVMConversionPatterns(converter, llvmPatterns);
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cf::populateControlFlowToLLVMConversionPatterns(converter, llvmPatterns);
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populateFuncToLLVMConversionPatterns(converter, llvmPatterns);
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populateFinalizeMemRefToLLVMConversionPatterns(converter, llvmPatterns);
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populateGpuToROCDLConversionPatterns(converter, llvmPatterns, runtime);
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LLVMConversionTarget target(getContext());
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configureGpuToROCDLConversionLegality(target);
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if (failed(applyPartialConversion(m, target, std::move(llvmPatterns))))
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signalPassFailure();
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// Manually rewrite known block size attributes so the LLVMIR translation
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// infrastructure can pick them up.
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m.walk([ctx](LLVM::LLVMFuncOp op) {
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if (auto blockSizes =
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op->removeAttr(gpu::GPUFuncOp::getKnownBlockSizeAttrName())
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.dyn_cast_or_null<DenseI32ArrayAttr>()) {
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op->setAttr(ROCDL::ROCDLDialect::getReqdWorkGroupSizeAttrName(),
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blockSizes);
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// Also set up the rocdl.flat_work_group_size attribute to prevent
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// conflicting metadata.
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uint32_t flatSize = 1;
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for (uint32_t size : blockSizes.asArrayRef()) {
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flatSize *= size;
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}
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StringAttr flatSizeAttr =
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StringAttr::get(ctx, Twine(flatSize) + "," + Twine(flatSize));
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op->setAttr(ROCDL::ROCDLDialect::getFlatWorkGroupSizeAttrName(),
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flatSizeAttr);
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}
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});
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}
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};
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} // namespace
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void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) {
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target.addIllegalOp<func::FuncOp>();
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target.addLegalDialect<::mlir::LLVM::LLVMDialect>();
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target.addLegalDialect<ROCDL::ROCDLDialect>();
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target.addIllegalDialect<gpu::GPUDialect>();
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target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp,
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LLVM::FCeilOp, LLVM::FFloorOp, LLVM::LogOp, LLVM::Log10Op,
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LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>();
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// TODO: Remove once we support replacing non-root ops.
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target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>();
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}
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template <typename OpTy>
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static void populateOpPatterns(LLVMTypeConverter &converter,
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RewritePatternSet &patterns, StringRef f32Func,
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StringRef f64Func) {
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patterns.add<ScalarizeVectorOpLowering<OpTy>>(converter);
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patterns.add<OpToFuncCallLowering<OpTy>>(converter, f32Func, f64Func);
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}
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void mlir::populateGpuToROCDLConversionPatterns(
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LLVMTypeConverter &converter, RewritePatternSet &patterns,
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mlir::gpu::amd::Runtime runtime) {
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using mlir::gpu::amd::Runtime;
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populateWithGenerated(patterns);
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patterns
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.add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp,
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ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>>(
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converter, gpu::GPUFuncOp::getKnownBlockSizeAttrName());
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patterns.add<GPUIndexIntrinsicOpLowering<
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gpu::BlockIdOp, ROCDL::BlockIdXOp, ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>>(
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converter, gpu::GPUFuncOp::getKnownGridSizeAttrName());
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patterns
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.add<GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp,
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ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>,
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GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp,
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ROCDL::GridDimYOp, ROCDL::GridDimZOp>,
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GPUReturnOpLowering>(converter);
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patterns.add<GPUFuncOpLowering>(
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converter,
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/*allocaAddrSpace=*/ROCDL::ROCDLDialect::kPrivateMemoryAddressSpace,
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/*workgroupAddrSpace=*/ROCDL::ROCDLDialect::kSharedMemoryAddressSpace,
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StringAttr::get(&converter.getContext(),
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ROCDL::ROCDLDialect::getKernelFuncAttrName()));
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if (Runtime::HIP == runtime) {
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patterns.add<GPUPrintfOpToHIPLowering>(converter);
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} else if (Runtime::OpenCL == runtime) {
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// Use address space = 4 to match the OpenCL definition of printf()
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patterns.add<GPUPrintfOpToLLVMCallLowering>(converter, /*addressSpace=*/4);
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}
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populateOpPatterns<math::AbsFOp>(converter, patterns, "__ocml_fabs_f32",
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"__ocml_fabs_f64");
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populateOpPatterns<math::AtanOp>(converter, patterns, "__ocml_atan_f32",
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"__ocml_atan_f64");
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populateOpPatterns<math::Atan2Op>(converter, patterns, "__ocml_atan2_f32",
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"__ocml_atan2_f64");
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populateOpPatterns<math::CbrtOp>(converter, patterns, "__ocml_cbrt_f32",
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"__ocml_cbrt_f64");
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populateOpPatterns<math::CeilOp>(converter, patterns, "__ocml_ceil_f32",
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"__ocml_ceil_f64");
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populateOpPatterns<math::CosOp>(converter, patterns, "__ocml_cos_f32",
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"__ocml_cos_f64");
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populateOpPatterns<math::ExpOp>(converter, patterns, "__ocml_exp_f32",
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"__ocml_exp_f64");
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populateOpPatterns<math::Exp2Op>(converter, patterns, "__ocml_exp2_f32",
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"__ocml_exp2_f64");
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populateOpPatterns<math::ExpM1Op>(converter, patterns, "__ocml_expm1_f32",
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"__ocml_expm1_f64");
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populateOpPatterns<math::FloorOp>(converter, patterns, "__ocml_floor_f32",
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"__ocml_floor_f64");
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populateOpPatterns<math::LogOp>(converter, patterns, "__ocml_log_f32",
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"__ocml_log_f64");
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populateOpPatterns<math::Log10Op>(converter, patterns, "__ocml_log10_f32",
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"__ocml_log10_f64");
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populateOpPatterns<math::Log1pOp>(converter, patterns, "__ocml_log1p_f32",
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"__ocml_log1p_f64");
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populateOpPatterns<math::Log2Op>(converter, patterns, "__ocml_log2_f32",
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"__ocml_log2_f64");
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populateOpPatterns<math::PowFOp>(converter, patterns, "__ocml_pow_f32",
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"__ocml_pow_f64");
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populateOpPatterns<math::RsqrtOp>(converter, patterns, "__ocml_rsqrt_f32",
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"__ocml_rsqrt_f64");
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populateOpPatterns<math::SinOp>(converter, patterns, "__ocml_sin_f32",
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"__ocml_sin_f64");
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populateOpPatterns<math::SqrtOp>(converter, patterns, "__ocml_sqrt_f32",
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"__ocml_sqrt_f64");
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populateOpPatterns<math::TanhOp>(converter, patterns, "__ocml_tanh_f32",
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"__ocml_tanh_f64");
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populateOpPatterns<math::TanOp>(converter, patterns, "__ocml_tan_f32",
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"__ocml_tan_f64");
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}
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std::unique_ptr<OperationPass<gpu::GPUModuleOp>>
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mlir::createLowerGpuOpsToROCDLOpsPass(const std::string &chipset,
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unsigned indexBitwidth,
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bool useBarePtrCallConv,
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gpu::amd::Runtime runtime) {
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return std::make_unique<LowerGpuOpsToROCDLOpsPass>(
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chipset, indexBitwidth, useBarePtrCallConv, runtime);
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}
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