72a218056d
This adds support for: * `muslabin32` (MIPS N32) * `muslabi64` (MIPS N64) * `muslf32` (LoongArch ILP32F/LP64F) * `muslsf` (LoongArch ILP32S/LP64S) As we start adding glibc/musl cross-compilation support for these targets in Zig, it would make our life easier if LLVM recognized these triples. I'm hoping this'll be uncontroversial since the same has already been done for `musleabi`, `musleabihf`, and `muslx32`. I intentionally left out a musl equivalent of `gnuf64` (LoongArch ILP32D/LP64D); my understanding is that Loongson ultimately settled on simply `gnu` for this much more common case, so there doesn't *seem* to be a particularly compelling reason to add a `muslf64` that's basically deprecated on arrival. Note: I don't have commit access.
457 lines
15 KiB
C++
457 lines
15 KiB
C++
//===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares Mips TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/TargetParser/Triple.h"
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namespace clang {
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namespace targets {
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class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
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void setDataLayout() {
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StringRef Layout;
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if (ABI == "o32")
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Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
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else if (ABI == "n32")
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Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
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else if (ABI == "n64")
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Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
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else
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llvm_unreachable("Invalid ABI");
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if (BigEndian)
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resetDataLayout(("E-" + Layout).str());
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else
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resetDataLayout(("e-" + Layout).str());
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}
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std::string CPU;
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bool IsMips16;
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bool IsMicromips;
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bool IsNan2008;
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bool IsAbs2008;
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bool IsSingleFloat;
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bool IsNoABICalls;
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bool CanUseBSDABICalls;
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enum MipsFloatABI { HardFloat, SoftFloat } FloatABI;
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enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
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bool HasMSA;
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bool DisableMadd4;
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bool UseIndirectJumpHazard;
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bool NoOddSpreg;
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protected:
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enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
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std::string ABI;
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public:
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MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
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: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
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IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
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IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
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DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
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UseIndirectJumpHazard(false), FPMode(FPXX) {
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TheCXXABI.set(TargetCXXABI::GenericMIPS);
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if (Triple.isMIPS32())
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setABI("o32");
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else if (Triple.isABIN32())
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setABI("n32");
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else
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setABI("n64");
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CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
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CanUseBSDABICalls = Triple.isOSFreeBSD() ||
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Triple.isOSOpenBSD();
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}
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bool isIEEE754_2008Default() const {
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return CPU == "mips32r6" || CPU == "mips64r6";
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}
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enum FPModeEnum getDefaultFPMode() const {
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if (CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64")
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return FP64;
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else if (CPU == "mips1")
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return FP32;
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else
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return FPXX;
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}
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bool isNan2008() const override { return IsNan2008; }
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bool processorSupportsGPR64() const;
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StringRef getABI() const override { return ABI; }
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bool setABI(const std::string &Name) override {
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if (Name == "o32") {
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setO32ABITypes();
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ABI = Name;
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return true;
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}
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if (Name == "n32") {
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setN32ABITypes();
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ABI = Name;
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return true;
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}
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if (Name == "n64") {
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setN64ABITypes();
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ABI = Name;
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return true;
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}
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return false;
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}
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void setO32ABITypes() {
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Int64Type = SignedLongLong;
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IntMaxType = Int64Type;
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LongDoubleFormat = &llvm::APFloat::IEEEdouble();
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LongDoubleWidth = LongDoubleAlign = 64;
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LongWidth = LongAlign = 32;
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
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PointerWidth = PointerAlign = 32;
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PtrDiffType = SignedInt;
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SizeType = UnsignedInt;
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SuitableAlign = 64;
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}
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void setN32N64ABITypes() {
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LongDoubleWidth = LongDoubleAlign = 128;
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LongDoubleFormat = &llvm::APFloat::IEEEquad();
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if (getTriple().isOSFreeBSD()) {
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LongDoubleWidth = LongDoubleAlign = 64;
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LongDoubleFormat = &llvm::APFloat::IEEEdouble();
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}
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
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SuitableAlign = 128;
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}
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void setN64ABITypes() {
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setN32N64ABITypes();
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if (getTriple().isOSOpenBSD()) {
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Int64Type = SignedLongLong;
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} else {
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Int64Type = SignedLong;
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}
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IntMaxType = Int64Type;
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LongWidth = LongAlign = 64;
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PointerWidth = PointerAlign = 64;
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PtrDiffType = SignedLong;
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SizeType = UnsignedLong;
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}
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void setN32ABITypes() {
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setN32N64ABITypes();
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Int64Type = SignedLongLong;
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IntMaxType = Int64Type;
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LongWidth = LongAlign = 32;
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PointerWidth = PointerAlign = 32;
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PtrDiffType = SignedInt;
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SizeType = UnsignedInt;
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}
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bool isValidCPUName(StringRef Name) const override;
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool setCPU(const std::string &Name) override {
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CPU = Name;
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return isValidCPUName(Name);
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}
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const std::string &getCPU() const { return CPU; }
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bool
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initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const override {
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if (CPU.empty())
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CPU = getCPU();
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if (CPU == "octeon")
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Features["mips64r2"] = Features["cnmips"] = true;
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else if (CPU == "octeon+")
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Features["mips64r2"] = Features["cnmips"] = Features["cnmipsp"] = true;
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else
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Features[CPU] = true;
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return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
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}
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unsigned getISARev() const;
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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bool hasFeature(StringRef Feature) const override;
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BuiltinVaListKind getBuiltinVaListKind() const override {
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return TargetInfo::VoidPtrBuiltinVaList;
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}
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ArrayRef<const char *> getGCCRegNames() const override {
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static const char *const GCCRegNames[] = {
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// CPU register names
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// Must match second column of GCCRegAliases
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"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",
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"$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20",
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"$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30",
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"$31",
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// Floating point register names
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"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
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"$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
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"$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
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"$f28", "$f29", "$f30", "$f31",
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// Hi/lo and condition register names
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"hi", "lo", "", "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5",
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"$fcc6", "$fcc7", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi",
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"$ac3lo",
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// MSA register names
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"$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9",
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"$w10", "$w11", "$w12", "$w13", "$w14", "$w15", "$w16", "$w17", "$w18",
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"$w19", "$w20", "$w21", "$w22", "$w23", "$w24", "$w25", "$w26", "$w27",
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"$w28", "$w29", "$w30", "$w31",
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// MSA control register names
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"$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
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"$msarequest", "$msamap", "$msaunmap"
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};
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return llvm::ArrayRef(GCCRegNames);
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}
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bool validateAsmConstraint(const char *&Name,
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TargetInfo::ConstraintInfo &Info) const override {
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switch (*Name) {
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default:
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return false;
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case 'r': // CPU registers.
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case 'd': // Equivalent to "r" unless generating MIPS16 code.
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case 'y': // Equivalent to "r", backward compatibility only.
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case 'c': // $25 for indirect jumps
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case 'l': // lo register
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case 'x': // hilo register pair
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Info.setAllowsRegister();
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return true;
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case 'f': // floating-point registers.
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Info.setAllowsRegister();
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return FloatABI != SoftFloat;
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case 'I': // Signed 16-bit constant
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case 'J': // Integer 0
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case 'K': // Unsigned 16-bit constant
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case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
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case 'M': // Constants not loadable via lui, addiu, or ori
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case 'N': // Constant -1 to -65535
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case 'O': // A signed 15-bit constant
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case 'P': // A constant between 1 go 65535
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return true;
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case 'R': // An address that can be used in a non-macro load or store
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Info.setAllowsMemory();
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return true;
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case 'Z':
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if (Name[1] == 'C') { // An address usable by ll, and sc.
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Info.setAllowsMemory();
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Name++; // Skip over 'Z'.
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return true;
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}
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return false;
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}
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}
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std::string convertConstraint(const char *&Constraint) const override {
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std::string R;
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switch (*Constraint) {
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case 'Z': // Two-character constraint; add "^" hint for later parsing.
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if (Constraint[1] == 'C') {
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R = std::string("^") + std::string(Constraint, 2);
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Constraint++;
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return R;
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}
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break;
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}
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return TargetInfo::convertConstraint(Constraint);
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}
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std::string_view getClobbers() const override {
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// In GCC, $1 is not widely used in generated code (it's used only in a few
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// specific situations), so there is no real need for users to add it to
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// the clobbers list if they want to use it in their inline assembly code.
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//
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// In LLVM, $1 is treated as a normal GPR and is always allocatable during
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// code generation, so using it in inline assembly without adding it to the
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// clobbers list can cause conflicts between the inline assembly code and
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// the surrounding generated code.
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//
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// Another problem is that LLVM is allowed to choose $1 for inline assembly
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// operands, which will conflict with the ".set at" assembler option (which
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// we use only for inline assembly, in order to maintain compatibility with
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// GCC) and will also conflict with the user's usage of $1.
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//
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// The easiest way to avoid these conflicts and keep $1 as an allocatable
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// register for generated code is to automatically clobber $1 for all inline
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// assembly code.
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//
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// FIXME: We should automatically clobber $1 only for inline assembly code
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// which actually uses it. This would allow LLVM to use $1 for inline
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// assembly operands if the user's assembly code doesn't use it.
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return "~{$1}";
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}
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bool handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) override {
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IsMips16 = false;
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IsMicromips = false;
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IsNan2008 = isIEEE754_2008Default();
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IsAbs2008 = isIEEE754_2008Default();
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IsSingleFloat = false;
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FloatABI = HardFloat;
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DspRev = NoDSP;
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NoOddSpreg = false;
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FPMode = getDefaultFPMode();
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bool OddSpregGiven = false;
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bool StrictAlign = false;
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bool FpGiven = false;
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for (const auto &Feature : Features) {
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if (Feature == "+single-float")
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IsSingleFloat = true;
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else if (Feature == "+soft-float")
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FloatABI = SoftFloat;
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else if (Feature == "+mips16")
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IsMips16 = true;
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else if (Feature == "+micromips")
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IsMicromips = true;
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else if (Feature == "+mips32r6" || Feature == "+mips64r6")
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HasUnalignedAccess = true;
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// We cannot be sure that the order of strict-align vs mips32r6.
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// Thus we need an extra variable here.
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else if (Feature == "+strict-align")
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StrictAlign = true;
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else if (Feature == "+dsp")
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DspRev = std::max(DspRev, DSP1);
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else if (Feature == "+dspr2")
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DspRev = std::max(DspRev, DSP2);
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else if (Feature == "+msa")
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HasMSA = true;
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else if (Feature == "+nomadd4")
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DisableMadd4 = true;
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else if (Feature == "+fp64") {
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FPMode = FP64;
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FpGiven = true;
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} else if (Feature == "-fp64") {
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FPMode = FP32;
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FpGiven = true;
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} else if (Feature == "+fpxx") {
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FPMode = FPXX;
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FpGiven = true;
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} else if (Feature == "+nan2008")
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IsNan2008 = true;
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else if (Feature == "-nan2008")
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IsNan2008 = false;
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else if (Feature == "+abs2008")
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IsAbs2008 = true;
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else if (Feature == "-abs2008")
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IsAbs2008 = false;
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else if (Feature == "+noabicalls")
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IsNoABICalls = true;
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else if (Feature == "+use-indirect-jump-hazard")
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UseIndirectJumpHazard = true;
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else if (Feature == "+nooddspreg") {
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NoOddSpreg = true;
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OddSpregGiven = false;
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} else if (Feature == "-nooddspreg") {
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NoOddSpreg = false;
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OddSpregGiven = true;
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}
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}
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if (FPMode == FPXX && !OddSpregGiven)
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NoOddSpreg = true;
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if (StrictAlign)
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HasUnalignedAccess = false;
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if (HasMSA && !FpGiven) {
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FPMode = FP64;
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Features.push_back("+fp64");
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}
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setDataLayout();
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return true;
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}
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int getEHDataRegisterNumber(unsigned RegNo) const override {
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if (RegNo == 0)
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return 4;
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if (RegNo == 1)
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return 5;
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return -1;
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}
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bool isCLZForZeroUndef() const override { return false; }
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ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
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static const TargetInfo::GCCRegAlias O32RegAliases[] = {
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{{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
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{{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
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{{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
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{{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
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{{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
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{{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
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{{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
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{{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
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{{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
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{{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
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{{"ra"}, "$31"}
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};
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static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
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{{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
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{{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
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{{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
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{{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
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{{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
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{{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
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{{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
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{{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
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{{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
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{{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
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{{"ra"}, "$31"}
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};
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if (ABI == "o32")
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return llvm::ArrayRef(O32RegAliases);
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return llvm::ArrayRef(NewABIRegAliases);
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}
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bool hasInt128Type() const override {
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return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
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}
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unsigned getUnwindWordWidth() const override;
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bool validateTarget(DiagnosticsEngine &Diags) const override;
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bool hasBitIntType() const override { return true; }
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std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
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return std::make_pair(32, 32);
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}
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};
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} // namespace targets
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} // namespace clang
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#endif // LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
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