3a14ffbae3
This adds intrinsics defined in ARM-software/acle#260 Doing this requires some changes to the GCS instruction definitions, as these intrinsics make use of how some instructions don't modify the input register when GCS is disabled, and they need to be correctly marked with mayLoad/mayStore/hasSideEffects for instruction selection to work.
57 lines
2.1 KiB
C
57 lines
2.1 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
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// RUN: %clang_cc1 -triple aarch64-eabi -target-feature +gcs -emit-llvm %s -o - | FileCheck %s
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#include <arm_acle.h>
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// CHECK-LABEL: define dso_local i64 @test_chkfeat
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// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[__FEATURES_ADDR_I:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 1, ptr [[__FEATURES_ADDR_I]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[__FEATURES_ADDR_I]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.aarch64.chkfeat(i64 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[__FEATURES_ADDR_I]], align 8
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// CHECK-NEXT: [[XOR_I:%.*]] = xor i64 [[TMP1]], [[TMP2]]
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// CHECK-NEXT: ret i64 [[XOR_I]]
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//
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uint64_t test_chkfeat() {
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return __chkfeat(_CHKFEAT_GCS);
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}
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// CHECK-LABEL: define dso_local ptr @test_gcspr
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// CHECK-SAME: () #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META2:![0-9]+]])
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// CHECK-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr
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// CHECK-NEXT: ret ptr [[TMP1]]
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//
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void *test_gcspr() {
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return __gcspr();
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}
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// CHECK-LABEL: define dso_local i64 @test_gcspopm
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// CHECK-SAME: () #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.aarch64.gcspopm(i64 0)
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// CHECK-NEXT: ret i64 [[TMP0]]
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//
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uint64_t test_gcspopm() {
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return __gcspopm();
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}
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// CHECK-LABEL: define dso_local ptr @test_gcsss
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// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[__STACK_ADDR_I:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8
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// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8
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// CHECK-NEXT: store ptr [[TMP0]], ptr [[__STACK_ADDR_I]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__STACK_ADDR_I]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = call ptr @llvm.aarch64.gcsss(ptr [[TMP1]])
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// CHECK-NEXT: ret ptr [[TMP2]]
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//
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const void *test_gcsss(const void *p) {
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return __gcsss(p);
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}
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