c4c9d4f306
Add support for the moveq instruction, which is both faster and smaller (1/2 to 1/3 the size) than a move with immediate to register. This change introduces the instruction, along with a set of pseudoinstructions to handle immediate moves to a register that is lowered post-RA. Pseudos are used as moveq can only write to the full register, which makes matching i8 and i16 immediate loads difficult in tablegen. Furthermore, selecting moveq before RA constrains that immediate to be moved into a data register, which may not be optimal. The bulk of this change are fixes to existing tests, which cover the new functionality sufficiently.
336 lines
12 KiB
C++
336 lines
12 KiB
C++
//===-- M68kExpandPseudo.cpp - Expand pseudo instructions -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains a pass that expands pseudo instructions into target
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/// instructions to allow proper scheduling, if-conversion, other late
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/// optimizations, or simply the encoding of the instructions.
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///
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//===----------------------------------------------------------------------===//
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#include "M68k.h"
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#include "M68kFrameLowering.h"
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#include "M68kInstrInfo.h"
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#include "M68kMachineFunction.h"
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#include "M68kSubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
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#include "llvm/IR/EHPersonalities.h"
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#include "llvm/IR/GlobalValue.h"
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using namespace llvm;
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#define DEBUG_TYPE "m68k-expand-pseudo"
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#define PASS_NAME "M68k pseudo instruction expansion pass"
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namespace {
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class M68kExpandPseudo : public MachineFunctionPass {
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public:
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static char ID;
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M68kExpandPseudo() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const M68kSubtarget *STI;
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const M68kInstrInfo *TII;
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const M68kRegisterInfo *TRI;
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const M68kMachineFunctionInfo *MFI;
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const M68kFrameLowering *FL;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
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bool ExpandMBB(MachineBasicBlock &MBB);
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};
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char M68kExpandPseudo::ID = 0;
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} // End anonymous namespace.
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INITIALIZE_PASS(M68kExpandPseudo, DEBUG_TYPE, PASS_NAME, false, false)
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/// If \p MBBI is a pseudo instruction, this method expands
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/// it to the corresponding (sequence of) actual instruction(s).
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/// \returns true if \p MBBI has been expanded.
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bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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MachineInstr &MI = *MBBI;
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MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
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unsigned Opcode = MI.getOpcode();
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DebugLoc DL = MBBI->getDebugLoc();
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/// TODO infer argument size to create less switch cases
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switch (Opcode) {
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default:
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return false;
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case M68k::MOVI8di:
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return TII->ExpandMOVI(MIB, MVT::i8);
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case M68k::MOVI16ri:
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return TII->ExpandMOVI(MIB, MVT::i16);
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case M68k::MOVI32ri:
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return TII->ExpandMOVI(MIB, MVT::i32);
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case M68k::MOVXd16d8:
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return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8);
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case M68k::MOVXd32d8:
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return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8);
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case M68k::MOVXd32d16:
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return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16);
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case M68k::MOVSXd16d8:
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return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8);
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case M68k::MOVSXd32d8:
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return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8);
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case M68k::MOVSXd32d16:
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return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16);
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case M68k::MOVZXd16d8:
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return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8);
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case M68k::MOVZXd32d8:
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return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i8);
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case M68k::MOVZXd32d16:
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return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16);
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case M68k::MOVSXd16j8:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i16,
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MVT::i8);
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case M68k::MOVSXd32j8:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i32,
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MVT::i8);
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case M68k::MOVSXd32j16:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV16rj), MVT::i32,
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MVT::i16);
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case M68k::MOVZXd16j8:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8dj), MVT::i16,
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MVT::i8);
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case M68k::MOVZXd32j8:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8dj), MVT::i32,
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MVT::i8);
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case M68k::MOVZXd32j16:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV16rj), MVT::i32,
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MVT::i16);
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case M68k::MOVSXd16p8:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dp), MVT::i16,
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MVT::i8);
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case M68k::MOVSXd32p8:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dp), MVT::i32,
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MVT::i8);
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case M68k::MOVSXd32p16:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV16rp), MVT::i32,
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MVT::i16);
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case M68k::MOVZXd16p8:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8dp), MVT::i16,
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MVT::i8);
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case M68k::MOVZXd32p8:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8dp), MVT::i32,
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MVT::i8);
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case M68k::MOVZXd32p16:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV16rp), MVT::i32,
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MVT::i16);
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case M68k::MOVSXd16f8:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8df), MVT::i16,
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MVT::i8);
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case M68k::MOVSXd32f8:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8df), MVT::i32,
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MVT::i8);
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case M68k::MOVSXd32f16:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV16rf), MVT::i32,
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MVT::i16);
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case M68k::MOVZXd16f8:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8df), MVT::i16,
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MVT::i8);
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case M68k::MOVZXd32f8:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8df), MVT::i32,
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MVT::i8);
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case M68k::MOVZXd32f16:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV16rf), MVT::i32,
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MVT::i16);
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case M68k::MOVSXd16q8:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dq), MVT::i16,
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MVT::i8);
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case M68k::MOVSXd32q8:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dq), MVT::i32,
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MVT::i8);
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case M68k::MOVSXd32q16:
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return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV16dq), MVT::i32,
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MVT::i16);
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case M68k::MOVZXd16q8:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8dq), MVT::i16,
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MVT::i8);
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case M68k::MOVZXd32q8:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8dq), MVT::i32,
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MVT::i8);
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case M68k::MOVZXd32q16:
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return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV16dq), MVT::i32,
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MVT::i16);
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case M68k::MOV8cd:
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return TII->ExpandCCR(MIB, /*IsToCCR=*/true);
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case M68k::MOV8dc:
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return TII->ExpandCCR(MIB, /*IsToCCR=*/false);
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case M68k::MOVM8jm_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32jm), /*IsRM=*/false);
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case M68k::MOVM16jm_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32jm), /*IsRM=*/false);
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case M68k::MOVM32jm_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32jm), /*IsRM=*/false);
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case M68k::MOVM8pm_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32pm), /*IsRM=*/false);
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case M68k::MOVM16pm_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32pm), /*IsRM=*/false);
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case M68k::MOVM32pm_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32pm), /*IsRM=*/false);
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case M68k::MOVM8mj_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true);
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case M68k::MOVM16mj_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true);
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case M68k::MOVM32mj_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true);
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case M68k::MOVM8mp_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true);
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case M68k::MOVM16mp_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true);
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case M68k::MOVM32mp_P:
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return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true);
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case M68k::TCRETURNq:
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case M68k::TCRETURNj: {
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MachineOperand &JumpTarget = MI.getOperand(0);
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MachineOperand &StackAdjust = MI.getOperand(1);
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assert(StackAdjust.isImm() && "Expecting immediate value.");
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// Adjust stack pointer.
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int StackAdj = StackAdjust.getImm();
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int MaxTCDelta = MFI->getTCReturnAddrDelta();
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int Offset = 0;
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assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
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// Incoporate the retaddr area.
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Offset = StackAdj - MaxTCDelta;
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assert(Offset >= 0 && "Offset should never be negative");
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if (Offset) {
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// Check for possible merge with preceding ADD instruction.
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Offset += FL->mergeSPUpdates(MBB, MBBI, true);
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FL->emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
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}
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// Jump to label or value in register.
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if (Opcode == M68k::TCRETURNq) {
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, DL, TII->get(M68k::TAILJMPq));
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if (JumpTarget.isGlobal()) {
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MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
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JumpTarget.getTargetFlags());
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} else {
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assert(JumpTarget.isSymbol());
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MIB.addExternalSymbol(JumpTarget.getSymbolName(),
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JumpTarget.getTargetFlags());
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}
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} else {
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BuildMI(MBB, MBBI, DL, TII->get(M68k::TAILJMPj))
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.addReg(JumpTarget.getReg(), RegState::Kill);
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}
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MachineInstr &NewMI = *std::prev(MBBI);
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NewMI.copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
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// Delete the pseudo instruction TCRETURN.
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MBB.erase(MBBI);
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return true;
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}
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case M68k::RET: {
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if (MBB.getParent()->getFunction().getCallingConv() ==
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CallingConv::M68k_INTR) {
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BuildMI(MBB, MBBI, DL, TII->get(M68k::RTE));
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} else if (int64_t StackAdj = MBBI->getOperand(0).getImm(); StackAdj == 0) {
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BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
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} else {
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// Copy return address from stack to a free address(A0 or A1) register
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// TODO check if pseudo expand uses free address register
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BuildMI(MBB, MBBI, DL, TII->get(M68k::MOV32aj), M68k::A1)
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.addReg(M68k::SP);
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// Adjust SP
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FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true);
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// Put the return address on stack
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BuildMI(MBB, MBBI, DL, TII->get(M68k::MOV32ja))
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.addReg(M68k::SP)
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.addReg(M68k::A1);
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// RTS
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BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
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}
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// FIXME: Can rest of the operands be ignored, if there is any?
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MBB.erase(MBBI);
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return true;
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}
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}
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llvm_unreachable("Previous switch has a fallthrough?");
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}
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/// Expand all pseudo instructions contained in \p MBB.
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/// \returns true if any expansion occurred for \p MBB.
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bool M68kExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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// MBBI may be invalidated by the expansion.
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= ExpandMI(MBB, MBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool M68kExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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STI = &MF.getSubtarget<M68kSubtarget>();
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TII = STI->getInstrInfo();
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TRI = STI->getRegisterInfo();
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MFI = MF.getInfo<M68kMachineFunctionInfo>();
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FL = STI->getFrameLowering();
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bool Modified = false;
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for (MachineBasicBlock &MBB : MF)
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Modified |= ExpandMBB(MBB);
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return Modified;
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}
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/// Returns an instance of the pseudo instruction expansion pass.
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FunctionPass *llvm::createM68kExpandPseudoPass() {
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return new M68kExpandPseudo();
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}
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