f0eb5587ce
This set of instructions was only supported by AMD chips starting in the K6-2 (introduced 1998), and before the "Bulldozer" family (2011). They were never much used, as they were effectively superseded by the more-widely-implemented SSE (first implemented on the AMD side in Athlon XP in 2001). This is being done as a predecessor towards general removal of MMX register usage. Since there is almost no usage of the 3DNow! intrinsics, and no modern hardware even implements them, simple removal seems like the best option. (Clang half originally uploaded in https://reviews.llvm.org/D94213) Works towards issue #41665 and issue #98272.
430 lines
15 KiB
C++
430 lines
15 KiB
C++
//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the X86 specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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#define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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#include "X86FrameLowering.h"
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#include "X86ISelLowering.h"
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#include "X86InstrInfo.h"
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#include "X86SelectionDAGInfo.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/TargetParser/Triple.h"
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#include <climits>
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#include <memory>
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#define GET_SUBTARGETINFO_HEADER
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#include "X86GenSubtargetInfo.inc"
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namespace llvm {
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class CallLowering;
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class GlobalValue;
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class InstructionSelector;
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class LegalizerInfo;
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class RegisterBankInfo;
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class StringRef;
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class TargetMachine;
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/// The X86 backend supports a number of different styles of PIC.
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///
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namespace PICStyles {
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enum class Style {
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StubPIC, // Used on i386-darwin in pic mode.
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GOT, // Used on 32 bit elf on when in pic mode.
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RIPRel, // Used on X86-64 when in pic mode.
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None // Set when not in pic mode.
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};
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} // end namespace PICStyles
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class X86Subtarget final : public X86GenSubtargetInfo {
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enum X86SSEEnum {
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NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512
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};
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/// Which PIC style to use
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PICStyles::Style PICStyle;
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const TargetMachine &TM;
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/// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
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X86SSEEnum X86SSELevel = NoSSE;
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool ATTRIBUTE = DEFAULT;
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#include "X86GenSubtargetInfo.inc"
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/// The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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Align stackAlignment = Align(4);
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Align TileConfigAlignment = Align(4);
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/// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
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///
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// FIXME: this is a known good value for Yonah. How about others?
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unsigned MaxInlineSizeThreshold = 128;
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/// What processor and OS we're targeting.
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Triple TargetTriple;
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/// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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/// Override the stack alignment.
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MaybeAlign StackAlignOverride;
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/// Preferred vector width from function attribute.
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unsigned PreferVectorWidthOverride;
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/// Resolved preferred vector width from function attribute and subtarget
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/// features.
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unsigned PreferVectorWidth = UINT32_MAX;
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/// Required vector width from function attribute.
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unsigned RequiredVectorWidth;
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X86SelectionDAGInfo TSInfo;
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// Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
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// X86TargetLowering needs.
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X86InstrInfo InstrInfo;
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X86TargetLowering TLInfo;
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X86FrameLowering FrameLowering;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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///
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X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
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const X86TargetMachine &TM, MaybeAlign StackAlignOverride,
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unsigned PreferVectorWidthOverride,
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unsigned RequiredVectorWidth);
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const X86TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const X86FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const X86RegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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unsigned getTileConfigSize() const { return 64; }
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Align getTileConfigAlignment() const { return TileConfigAlignment; }
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/// Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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Align getStackAlignment() const { return stackAlignment; }
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/// Returns the maximum memset / memcpy size
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/// that still makes it profitable to inline the call.
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unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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/// Methods used by Global ISel
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const CallLowering *getCallLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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private:
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/// Initialize the full set of dependencies so we can use an initializer
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/// list for X86Subtarget.
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X86Subtarget &initializeSubtargetDependencies(StringRef CPU,
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StringRef TuneCPU,
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StringRef FS);
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void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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public:
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool GETTER() const { return ATTRIBUTE; }
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#include "X86GenSubtargetInfo.inc"
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/// Is this x86_64 with the ILP32 programming model (x32 ABI)?
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bool isTarget64BitILP32() const {
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return Is64Bit && (TargetTriple.isX32() || TargetTriple.isOSNaCl());
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}
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/// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
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bool isTarget64BitLP64() const {
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return Is64Bit && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl());
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}
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PICStyles::Style getPICStyle() const { return PICStyle; }
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void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
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bool canUseCMPXCHG8B() const { return hasCX8(); }
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bool canUseCMPXCHG16B() const {
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// CX16 is just the CPUID bit, instruction requires 64-bit mode too.
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return hasCX16() && is64Bit();
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}
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// SSE codegen depends on cmovs, and all SSE1+ processors support them.
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// All 64-bit processors support cmov.
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bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); }
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bool hasSSE1() const { return X86SSELevel >= SSE1; }
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bool hasSSE2() const { return X86SSELevel >= SSE2; }
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bool hasSSE3() const { return X86SSELevel >= SSE3; }
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bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
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bool hasSSE41() const { return X86SSELevel >= SSE41; }
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bool hasSSE42() const { return X86SSELevel >= SSE42; }
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bool hasAVX() const { return X86SSELevel >= AVX; }
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bool hasAVX2() const { return X86SSELevel >= AVX2; }
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bool hasAVX512() const { return X86SSELevel >= AVX512; }
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bool hasInt256() const { return hasAVX2(); }
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bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
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bool hasPrefetchW() const {
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// The PREFETCHW instruction was added with 3DNow but later CPUs gave it
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// its own CPUID bit as part of deprecating 3DNow.
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return hasPRFCHW();
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}
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bool hasSSEPrefetch() const {
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// We also implicitly enable these when we have a write prefix supporting
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// cache level OR if we have prfchw.
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return hasSSE1() || hasPRFCHW() || hasPREFETCHI();
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}
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bool canUseLAHFSAHF() const { return hasLAHFSAHF64() || !is64Bit(); }
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// These are generic getters that OR together all of the thunk types
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// supported by the subtarget. Therefore useIndirectThunk*() will return true
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// if any respective thunk feature is enabled.
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bool useIndirectThunkCalls() const {
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return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity();
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}
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bool useIndirectThunkBranches() const {
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return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity();
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}
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unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
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unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
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// Helper functions to determine when we should allow widening to 512-bit
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// during codegen.
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// TODO: Currently we're always allowing widening on CPUs without VLX,
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// because for many cases we don't have a better option.
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bool canExtendTo512DQ() const {
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return hasAVX512() && hasEVEX512() &&
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(!hasVLX() || getPreferVectorWidth() >= 512);
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}
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bool canExtendTo512BW() const {
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return hasBWI() && canExtendTo512DQ();
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}
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bool hasNoDomainDelay() const { return NoDomainDelay; }
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bool hasNoDomainDelayMov() const {
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return hasNoDomainDelay() || NoDomainDelayMov;
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}
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bool hasNoDomainDelayBlend() const {
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return hasNoDomainDelay() || NoDomainDelayBlend;
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}
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bool hasNoDomainDelayShuffle() const {
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return hasNoDomainDelay() || NoDomainDelayShuffle;
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}
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// If there are no 512-bit vectors and we prefer not to use 512-bit registers,
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// disable them in the legalizer.
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bool useAVX512Regs() const {
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return hasAVX512() && hasEVEX512() &&
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(canExtendTo512DQ() || RequiredVectorWidth > 256);
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}
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bool useLight256BitInstructions() const {
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return getPreferVectorWidth() >= 256 || AllowLight256Bit;
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}
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bool useBWIRegs() const {
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return hasBWI() && useAVX512Regs();
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}
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bool isXRaySupported() const override { return is64Bit(); }
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/// Use clflush if we have SSE2 or we're on x86-64 (even if we asked for
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/// no-sse2). There isn't any reason to disable it if the target processor
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/// supports it.
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bool hasCLFLUSH() const { return hasSSE2() || is64Bit(); }
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/// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
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/// no-sse2). There isn't any reason to disable it if the target processor
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/// supports it.
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bool hasMFence() const { return hasSSE2() || is64Bit(); }
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
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bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
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bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
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bool isTargetPS() const { return TargetTriple.isPS(); }
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
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bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
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bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
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bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
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bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
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bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
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bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
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bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
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bool isTargetWindowsMSVC() const {
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return TargetTriple.isWindowsMSVCEnvironment();
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}
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bool isTargetWindowsCoreCLR() const {
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return TargetTriple.isWindowsCoreCLREnvironment();
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}
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bool isTargetWindowsCygwin() const {
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return TargetTriple.isWindowsCygwinEnvironment();
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}
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bool isTargetWindowsGNU() const {
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return TargetTriple.isWindowsGNUEnvironment();
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}
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bool isTargetWindowsItanium() const {
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return TargetTriple.isWindowsItaniumEnvironment();
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}
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bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
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bool isOSWindows() const { return TargetTriple.isOSWindows(); }
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bool isTargetWin64() const { return Is64Bit && isOSWindows(); }
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bool isTargetWin32() const { return !Is64Bit && isOSWindows(); }
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bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; }
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bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; }
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bool isPICStyleStubPIC() const {
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return PICStyle == PICStyles::Style::StubPIC;
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}
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bool isPositionIndependent() const;
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bool isCallingConvWin64(CallingConv::ID CC) const {
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switch (CC) {
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// On Win64, all these conventions just use the default convention.
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case CallingConv::C:
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case CallingConv::Fast:
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case CallingConv::Tail:
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case CallingConv::Swift:
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case CallingConv::SwiftTail:
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case CallingConv::X86_FastCall:
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case CallingConv::X86_StdCall:
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case CallingConv::X86_ThisCall:
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case CallingConv::X86_VectorCall:
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case CallingConv::Intel_OCL_BI:
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return isTargetWin64();
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// This convention allows using the Win64 convention on other targets.
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case CallingConv::Win64:
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return true;
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// This convention allows using the SysV convention on Windows targets.
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case CallingConv::X86_64_SysV:
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return false;
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// Otherwise, who knows what this is.
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default:
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return false;
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}
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}
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/// Classify a global variable reference for the current subtarget according
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/// to how we should reference it in a non-pcrel context.
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unsigned char classifyLocalReference(const GlobalValue *GV) const;
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unsigned char classifyGlobalReference(const GlobalValue *GV,
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const Module &M) const;
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unsigned char classifyGlobalReference(const GlobalValue *GV) const;
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/// Classify a global function reference for the current subtarget.
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unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
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const Module &M) const;
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unsigned char
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classifyGlobalFunctionReference(const GlobalValue *GV) const override;
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/// Classify a blockaddress reference for the current subtarget according to
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/// how we should reference it in a non-pcrel context.
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unsigned char classifyBlockAddressReference() const;
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/// Return true if the subtarget allows calls to immediate address.
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bool isLegalToCallImmediateAddr() const;
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/// Return whether FrameLowering should always set the "extended frame
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/// present" bit in FP, or set it based on a symbol in the runtime.
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bool swiftAsyncContextIsDynamicallySet() const {
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// Older OS versions (particularly system unwinders) are confused by the
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// Swift extended frame, so when building code that might be run on them we
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// must dynamically query the concurrency library to determine whether
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// extended frames should be flagged as present.
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const Triple &TT = getTargetTriple();
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unsigned Major = TT.getOSVersion().getMajor();
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switch(TT.getOS()) {
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default:
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return false;
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case Triple::IOS:
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case Triple::TvOS:
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return Major < 15;
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case Triple::WatchOS:
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return Major < 8;
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case Triple::MacOSX:
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case Triple::Darwin:
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return Major < 12;
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}
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}
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/// If we are using indirect thunks, we need to expand indirectbr to avoid it
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/// lowering to an actual indirect jump.
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bool enableIndirectBrExpand() const override {
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return useIndirectThunkBranches();
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}
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/// Enable the MachineScheduler pass for all X86 subtargets.
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bool enableMachineScheduler() const override { return true; }
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bool enableEarlyIfConversion() const override;
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void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
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&Mutations) const override;
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AntiDepBreakMode getAntiDepBreakMode() const override {
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return TargetSubtargetInfo::ANTIDEP_CRITICAL;
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}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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