d58bd21150
When a pattern is matched in TableGen, a check is run called isObviouslySafeToFold(). One of the condition that it checks for is whether the instructions that are being matched are consecutive, so the instruction's insertion point does not change. This patch allows the movement of the insertion point of a load instruction if none of the intervening instructions are stores or have side-effects.
819 lines
22 KiB
YAML
819 lines
22 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @load_s64_gpr(ptr %addr) { ret void }
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define void @load_s32_gpr(ptr %addr) { ret void }
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define void @load_s16_gpr_anyext(ptr %addr) { ret void }
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define void @load_s16_gpr(ptr %addr) { ret void }
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define void @load_s8_gpr_anyext(ptr %addr) { ret void }
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define void @load_s8_gpr(ptr %addr) { ret void }
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define void @load_fi_s64_gpr() {
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%ptr0 = alloca i64
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ret void
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}
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define void @load_gep_128_s64_gpr(ptr %addr) { ret void }
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define void @load_gep_512_s32_gpr(ptr %addr) { ret void }
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define void @load_gep_64_s16_gpr(ptr %addr) { ret void }
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define void @load_gep_1_s8_gpr(ptr %addr) { ret void }
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define void @load_s64_fpr(ptr %addr) { ret void }
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define void @load_s32_fpr(ptr %addr) { ret void }
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define void @load_s16_fpr(ptr %addr) { ret void }
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define void @load_s8_fpr(ptr %addr) { ret void }
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define void @load_gep_8_s64_fpr(ptr %addr) { ret void }
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define void @load_gep_16_s32_fpr(ptr %addr) { ret void }
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define void @load_gep_64_s16_fpr(ptr %addr) { ret void }
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define void @load_gep_32_s8_fpr(ptr %addr) { ret void }
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define void @load_v2s32(ptr %addr) { ret void }
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define void @load_v2s64(ptr %addr) { ret void }
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define void @load_4xi16(ptr %ptr) { ret void }
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define void @load_4xi32(ptr %ptr) { ret void }
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define void @load_8xi16(ptr %ptr) { ret void }
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define void @load_16xi8(ptr %ptr) { ret void }
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define void @anyext_on_fpr() { ret void }
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define void @anyext_on_fpr8() { ret void }
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define void @load_s32_gpr_LD1() { ret void }
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define void @load_s32_gpr_GIM() { ret void }
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...
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---
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name: load_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s64_gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load (s64) from %ir.addr)
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; CHECK-NEXT: $x0 = COPY [[LDRXui]]
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%0(p0) = COPY $x0
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%1(s64) = G_LOAD %0 :: (load (s64) from %ir.addr)
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$x0 = COPY %1(s64)
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...
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---
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name: load_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s32_gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from %ir.addr)
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; CHECK-NEXT: $w0 = COPY [[LDRWui]]
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%0(p0) = COPY $x0
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%1(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)
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$w0 = COPY %1(s32)
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...
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---
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name: load_s16_gpr_anyext
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s16_gpr_anyext
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
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; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_LOAD %0 :: (load (s16) from %ir.addr)
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$w0 = COPY %1(s32)
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...
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---
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name: load_s16_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s16_gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
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; CHECK-NEXT: $w0 = COPY [[COPY1]]
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%0(p0) = COPY $x0
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%1(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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$w0 = COPY %2(s32)
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...
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---
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name: load_s8_gpr_anyext
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s8_gpr_anyext
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)
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; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_LOAD %0 :: (load (s8) from %ir.addr)
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$w0 = COPY %1(s32)
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...
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---
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name: load_s8_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s8_gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
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; CHECK-NEXT: $w0 = COPY [[COPY1]]
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%0(p0) = COPY $x0
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%1(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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$w0 = COPY %2(s32)
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...
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---
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name: load_fi_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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stack:
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- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_fi_s64_gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load (s64))
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; CHECK-NEXT: $x0 = COPY [[LDRXui]]
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%0(p0) = G_FRAME_INDEX %stack.0.ptr0
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%1(s64) = G_LOAD %0 :: (load (s64))
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$x0 = COPY %1(s64)
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...
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---
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name: load_gep_128_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_gep_128_s64_gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load (s64) from %ir.addr)
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; CHECK-NEXT: $x0 = COPY [[LDRXui]]
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%0(p0) = COPY $x0
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%1(s64) = G_CONSTANT i64 128
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%2(p0) = G_PTR_ADD %0, %1
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%3(s64) = G_LOAD %2 :: (load (s64) from %ir.addr)
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$x0 = COPY %3
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...
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---
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name: load_gep_512_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_gep_512_s32_gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load (s32) from %ir.addr)
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; CHECK-NEXT: $w0 = COPY [[LDRWui]]
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%0(p0) = COPY $x0
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%1(s64) = G_CONSTANT i64 512
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%2(p0) = G_PTR_ADD %0, %1
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%3(s32) = G_LOAD %2 :: (load (s32) from %ir.addr)
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$w0 = COPY %3
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...
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---
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name: load_gep_64_s16_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_gep_64_s16_gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load (s16) from %ir.addr)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
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; CHECK-NEXT: $w0 = COPY [[COPY1]]
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%0(p0) = COPY $x0
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%1(s64) = G_CONSTANT i64 64
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%2(p0) = G_PTR_ADD %0, %1
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%3(s16) = G_LOAD %2 :: (load (s16) from %ir.addr)
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%4:gpr(s32) = G_ANYEXT %3
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$w0 = COPY %4
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...
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---
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name: load_gep_1_s8_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_gep_1_s8_gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load (s8) from %ir.addr)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
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; CHECK-NEXT: $w0 = COPY [[COPY1]]
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%0(p0) = COPY $x0
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%1(s64) = G_CONSTANT i64 1
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%2(p0) = G_PTR_ADD %0, %1
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%3(s8) = G_LOAD %2 :: (load (s8) from %ir.addr)
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%4:gpr(s32) = G_ANYEXT %3
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$w0 = COPY %4
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...
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---
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name: load_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s64_fpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (s64) from %ir.addr)
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; CHECK-NEXT: $d0 = COPY [[LDRDui]]
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%0(p0) = COPY $x0
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%1(s64) = G_LOAD %0 :: (load (s64) from %ir.addr)
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$d0 = COPY %1(s64)
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...
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---
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name: load_s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s32_fpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load (s32) from %ir.addr)
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; CHECK-NEXT: $s0 = COPY [[LDRSui]]
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%0(p0) = COPY $x0
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%1(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)
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$s0 = COPY %1(s32)
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...
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---
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name: load_s16_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s16_fpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16) from %ir.addr)
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; CHECK-NEXT: $h0 = COPY [[LDRHui]]
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%0(p0) = COPY $x0
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%1(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
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$h0 = COPY %1(s16)
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...
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---
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name: load_s8_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s8_fpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8) from %ir.addr)
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; CHECK-NEXT: $b0 = COPY [[LDRBui]]
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%0(p0) = COPY $x0
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%1(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)
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$b0 = COPY %1(s8)
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...
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---
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name: load_gep_8_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_gep_8_s64_fpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load (s64) from %ir.addr)
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; CHECK-NEXT: $d0 = COPY [[LDRDui]]
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%0(p0) = COPY $x0
|
|
%1(s64) = G_CONSTANT i64 8
|
|
%2(p0) = G_PTR_ADD %0, %1
|
|
%3(s64) = G_LOAD %2 :: (load (s64) from %ir.addr)
|
|
$d0 = COPY %3
|
|
...
|
|
|
|
---
|
|
name: load_gep_16_s32_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
- { id: 3, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: load_gep_16_s32_fpr
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load (s32) from %ir.addr)
|
|
; CHECK-NEXT: $s0 = COPY [[LDRSui]]
|
|
%0(p0) = COPY $x0
|
|
%1(s64) = G_CONSTANT i64 16
|
|
%2(p0) = G_PTR_ADD %0, %1
|
|
%3(s32) = G_LOAD %2 :: (load (s32) from %ir.addr)
|
|
$s0 = COPY %3
|
|
...
|
|
|
|
---
|
|
name: load_gep_64_s16_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
- { id: 3, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: load_gep_64_s16_fpr
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load (s16) from %ir.addr)
|
|
; CHECK-NEXT: $h0 = COPY [[LDRHui]]
|
|
%0(p0) = COPY $x0
|
|
%1(s64) = G_CONSTANT i64 64
|
|
%2(p0) = G_PTR_ADD %0, %1
|
|
%3(s16) = G_LOAD %2 :: (load (s16) from %ir.addr)
|
|
$h0 = COPY %3
|
|
...
|
|
|
|
---
|
|
name: load_gep_32_s8_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
- { id: 3, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: load_gep_32_s8_fpr
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load (s8) from %ir.addr)
|
|
; CHECK-NEXT: $b0 = COPY [[LDRBui]]
|
|
%0(p0) = COPY $x0
|
|
%1(s64) = G_CONSTANT i64 32
|
|
%2(p0) = G_PTR_ADD %0, %1
|
|
%3(s8) = G_LOAD %2 :: (load (s8) from %ir.addr)
|
|
$b0 = COPY %3
|
|
...
|
|
---
|
|
name: load_v2s32
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: load_v2s32
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x s32>) from %ir.addr)
|
|
; CHECK-NEXT: $d0 = COPY [[LDRDui]]
|
|
%0(p0) = COPY $x0
|
|
%1(<2 x s32>) = G_LOAD %0 :: (load (<2 x s32>) from %ir.addr)
|
|
$d0 = COPY %1(<2 x s32>)
|
|
...
|
|
---
|
|
name: load_v2s64
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: fpr }
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: load_v2s64
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>) from %ir.addr)
|
|
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
|
|
%0(p0) = COPY $x0
|
|
%1(<2 x s64>) = G_LOAD %0 :: (load (<2 x s64>) from %ir.addr)
|
|
$q0 = COPY %1(<2 x s64>)
|
|
...
|
|
---
|
|
name: load_4xi16
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: fpr }
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: load_4xi16
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<4 x s16>) from %ir.ptr)
|
|
; CHECK-NEXT: $d0 = COPY [[LDRDui]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:gpr(p0) = COPY $x0
|
|
%1:fpr(<4 x s16>) = G_LOAD %0(p0) :: (load (<4 x s16>) from %ir.ptr)
|
|
$d0 = COPY %1(<4 x s16>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: load_4xi32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: fpr }
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: load_4xi32
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x s32>) from %ir.ptr)
|
|
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:gpr(p0) = COPY $x0
|
|
%1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.ptr)
|
|
$q0 = COPY %1(<4 x s32>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: load_8xi16
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: fpr }
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: load_8xi16
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>) from %ir.ptr)
|
|
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:gpr(p0) = COPY $x0
|
|
%1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.ptr)
|
|
$q0 = COPY %1(<8 x s16>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: load_16xi8
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: fpr }
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: load_16xi8
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>) from %ir.ptr)
|
|
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:gpr(p0) = COPY $x0
|
|
%1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.ptr)
|
|
$q0 = COPY %1(<16 x s8>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: anyext_on_fpr
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$x0' }
|
|
- { reg: '$x1' }
|
|
- { reg: '$x2' }
|
|
- { reg: '$w3' }
|
|
frameInfo:
|
|
maxAlignment: 1
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.1:
|
|
liveins: $w3, $x0, $x1, $x2
|
|
|
|
; CHECK-LABEL: name: anyext_on_fpr
|
|
; CHECK: liveins: $w3, $x0, $x1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16))
|
|
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRHui]], %subreg.hsub
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
|
|
; CHECK-NEXT: $w0 = COPY [[COPY1]]
|
|
; CHECK-NEXT: RET_ReallyLR
|
|
%0:gpr(p0) = COPY $x0
|
|
%16:fpr(s32) = G_LOAD %0(p0) :: (load (s16))
|
|
%24:gpr(s32) = COPY %16(s32)
|
|
$w0 = COPY %24(s32)
|
|
RET_ReallyLR
|
|
|
|
...
|
|
---
|
|
name: anyext_on_fpr8
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$x0' }
|
|
- { reg: '$x1' }
|
|
- { reg: '$x2' }
|
|
- { reg: '$w3' }
|
|
frameInfo:
|
|
maxAlignment: 1
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.1:
|
|
liveins: $w3, $x0, $x1, $x2
|
|
|
|
; CHECK-LABEL: name: anyext_on_fpr8
|
|
; CHECK: liveins: $w3, $x0, $x1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8))
|
|
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRBui]], %subreg.bsub
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
|
|
; CHECK-NEXT: $w0 = COPY [[COPY1]]
|
|
; CHECK-NEXT: RET_ReallyLR
|
|
%0:gpr(p0) = COPY $x0
|
|
%16:fpr(s32) = G_LOAD %0(p0) :: (load (s8))
|
|
%24:gpr(s32) = COPY %16(s32)
|
|
$w0 = COPY %24(s32)
|
|
RET_ReallyLR
|
|
|
|
...
|
|
---
|
|
name: load_s32_gpr_LD1
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $x0
|
|
|
|
; CHECK-LABEL: name: load_s32_gpr_LD1
|
|
; CHECK: liveins: $q0, $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LD1i32_:%[0-9]+]]:fpr128 = LD1i32 [[COPY]], 0, [[COPY1]] :: (load (s32))
|
|
; CHECK-NEXT: $q0 = COPY [[LD1i32_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<4 x s32>) = COPY $q0
|
|
%1:gpr(p0) = COPY $x0
|
|
%2:fpr(s32) = G_LOAD %1(p0) :: (load (s32))
|
|
%3:gpr(s32) = G_CONSTANT i32 3
|
|
%5:gpr(s64) = G_CONSTANT i64 0
|
|
%4:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %2(s32), %5(s64)
|
|
$q0 = COPY %4(<4 x s32>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
|
|
name: load_s32_gpr_GIM
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $x0
|
|
;This test should not select an LD1 instruction as there is a store instruction between G_INSERT_VECTOR_ELT and G_LOAD
|
|
; CHECK-LABEL: name: load_s32_gpr_GIM
|
|
; CHECK: liveins: $q0, $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY1]], 0 :: (load (s32))
|
|
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
|
|
; CHECK-NEXT: STRWui [[MOVi32imm]], [[COPY1]], 0 :: (store (s32))
|
|
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRSui]], %subreg.ssub
|
|
; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY]], 0, [[INSERT_SUBREG]], 0
|
|
; CHECK-NEXT: $q0 = COPY [[INSvi32lane]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<4 x s32>) = COPY $q0
|
|
%1:gpr(p0) = COPY $x0
|
|
%2:fpr(s32) = G_LOAD %1(p0) :: (load (s32))
|
|
%3:gpr(s32) = G_CONSTANT i32 3
|
|
G_STORE %3(s32), %1(p0) :: (store (s32))
|
|
%5:gpr(s64) = G_CONSTANT i64 0
|
|
%4:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %2(s32), %5(s64)
|
|
$q0 = COPY %4(<4 x s32>)
|
|
RET_ReallyLR implicit $q0
|
|
...
|