c83f23d6ab
The existing heuristics were assuming that every core behaves like an Apple A7, where any extend/shift costs an extra micro-op... but in reality, nothing else behaves like that. On some older Cortex designs, shifts by 1 or 4 cost extra, but all other shifts/extensions are free. On all other cores, as far as I can tell, all shifts/extensions for integer loads are free (i.e. the same cost as an unshifted load). To reflect this, this patch: - Enables aggressive folding of shifts into loads by default. - Removes the old AddrLSLFast feature, since it applies to everything except A7 (and even if you are explicitly targeting A7, we want to assume extensions are free because the code will almost always run on a newer core). - Adds a new feature AddrLSLSlow14 that applies specifically to the Cortex cores where shifts by 1 or 4 cost extra. I didn't add support for AddrLSLSlow14 on the GlobalISel side because it would require a bunch of refactoring to work correctly. Someone can pick this up as a followup.
146 lines
5.1 KiB
LLVM
146 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=arm64-apple-macosx -o - %s | FileCheck %s
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%struct.zot = type { ptr, i32, ptr, ptr, i32, i32, i32, i32, i32, i32 }
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; FIXME: currently the AND is performed on 64 bit unnecessarily.
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; Test cases where an AND is extended from i32 -> i64 which is free. Make
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; sure the extends do not get moved to the arguments, which would perform the
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; AND on 64 bits unnecessarily.
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define void @avoid_promotion_1_and(ptr nocapture noundef %arg, ptr %p) {
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; CHECK-LABEL: avoid_promotion_1_and:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: ldr w8, [x0, #52]
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; CHECK-NEXT: mov w9, #10 ; =0xa
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; CHECK-NEXT: LBB0_1: ; %bb8
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmp w8, #3
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; CHECK-NEXT: b.lo LBB0_1
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; CHECK-NEXT: ; %bb.2: ; %bb9
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; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: ldr w10, [x0, #32]
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; CHECK-NEXT: ldr w11, [x1, #76]
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; CHECK-NEXT: ldr w12, [x1]
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; CHECK-NEXT: eor w10, w10, w11
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; CHECK-NEXT: and w10, w10, w12
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; CHECK-NEXT: str w10, [x0, #32]
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; CHECK-NEXT: strh w9, [x1, w10, uxtw #1]
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; CHECK-NEXT: b LBB0_1
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bb:
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%gep = getelementptr inbounds %struct.zot, ptr %arg, i64 0, i32 9
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%l = load i32, ptr %gep, align 4
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%icmp = icmp ugt i32 %l, 2
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%gep1 = getelementptr inbounds %struct.zot, ptr %arg, i64 0, i32 4
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%gep2 = getelementptr inbounds %struct.zot, ptr %arg, i64 0, i32 7
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br label %bb8
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bb8: ; preds = %bb27, %bb
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br i1 %icmp, label %bb9, label %bb27
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bb9: ; preds = %bb8
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%l10 = load i32, ptr %gep1, align 8
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%gep14 = getelementptr inbounds i32, ptr %p, i64 19
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%l15 = load i32, ptr %gep14, align 1
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%xor = xor i32 %l10, %l15
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%l17 = load i32, ptr %p, align 8
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%and = and i32 %xor, %l17
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store i32 %and, ptr %gep1, align 8
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%zext19 = zext i32 %and to i64
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%gep20 = getelementptr inbounds i16, ptr %p, i64 %zext19
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store i16 10, ptr %gep20, align 2
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br label %bb27
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bb27: ; preds = %bb9, %bb8
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br label %bb8
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}
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define void @avoid_promotion_2_and(ptr nocapture noundef %arg) {
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; CHECK-LABEL: avoid_promotion_2_and:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: add x8, x0, #32
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; CHECK-NEXT: b LBB1_2
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; CHECK-NEXT: LBB1_1: ; %latch
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; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: cmp w9, #2
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; CHECK-NEXT: add x8, x8, #56
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; CHECK-NEXT: b.ls LBB1_4
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; CHECK-NEXT: LBB1_2: ; %loop
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr w9, [x8, #20]
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; CHECK-NEXT: cmp w9, #3
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; CHECK-NEXT: b.lo LBB1_1
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; CHECK-NEXT: ; %bb.3: ; %then
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; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: ldp w13, w12, [x8, #12]
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; CHECK-NEXT: ldr w10, [x8]
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; CHECK-NEXT: ldr x11, [x0]
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; CHECK-NEXT: ldr w14, [x8, #8]
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; CHECK-NEXT: lsl w10, w10, w13
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; CHECK-NEXT: ldrb w11, [x11, x12]
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; CHECK-NEXT: eor w10, w10, w11
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; CHECK-NEXT: ldur w11, [x8, #-24]
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; CHECK-NEXT: and w10, w10, w14
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; CHECK-NEXT: ldp x14, x13, [x8, #-16]
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; CHECK-NEXT: str w10, [x8]
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; CHECK-NEXT: and w11, w11, w12
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; CHECK-NEXT: ldrh w15, [x13, w10, uxtw #1]
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; CHECK-NEXT: strh w15, [x14, w11, uxtw #1]
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; CHECK-NEXT: strh w12, [x13, w10, uxtw #1]
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; CHECK-NEXT: b LBB1_1
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; CHECK-NEXT: LBB1_4: ; %exit
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; CHECK-NEXT: ret
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entry:
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br label %loop
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loop:
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%p = phi i64 [ 0, %entry ], [ %p.next, %latch ]
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%gep = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 9
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%l = load i32, ptr %gep, align 4
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%icmp = icmp ugt i32 %l, 2
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%gep1 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 4
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%gep2 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 7
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%gep3 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 8
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%gep4 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 6
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%gep5 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 3
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%gep6 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 2
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%gep7 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 1
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br i1 %icmp, label %then, label %latch
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then:
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%l10 = load i32, ptr %gep1, align 8
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%l11 = load i32, ptr %gep2, align 4
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%shl = shl i32 %l10, %l11
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%l12 = load ptr, ptr %arg, align 8
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%l13 = load i32, ptr %gep3, align 8
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%zext = zext i32 %l13 to i64
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%gep14 = getelementptr inbounds i8, ptr %l12, i64 %zext
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%l15 = load i8, ptr %gep14, align 1
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%zext16 = zext i8 %l15 to i32
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%xor = xor i32 %shl, %zext16
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%l17 = load i32, ptr %gep4, align 8
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%and = and i32 %xor, %l17
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store i32 %and, ptr %gep1, align 8
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%l18 = load ptr, ptr %gep5, align 8
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%zext19 = zext i32 %and to i64
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%gep20 = getelementptr inbounds i16, ptr %l18, i64 %zext19
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%l21 = load i16, ptr %gep20, align 2
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%l22 = load ptr, ptr %gep6, align 8
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%l23 = load i32, ptr %gep7, align 8
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%and24 = and i32 %l23, %l13
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%zext25 = zext i32 %and24 to i64
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%gep26 = getelementptr inbounds i16, ptr %l22, i64 %zext25
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store i16 %l21, ptr %gep26, align 2
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%trunc = trunc i32 %l13 to i16
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store i16 %trunc, ptr %gep20, align 2
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br label %latch
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latch:
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%p.next = add i64 %p, 1
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br i1 %icmp, label %loop, label %exit
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exit:
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ret void
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}
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