8d49ce1764
This hooks up G_INTRINSIC_LLRINT instructions, very similar to the lrint nodes that already exist. On AArch64 they are treated the same as lrint with the default return types.
68 lines
2.3 KiB
LLVM
68 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOFP16
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; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-FP16
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; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK-NOFP16
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; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK-FP16
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define i16 @testmhhs(half %x) {
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; CHECK-NOFP16-LABEL: testmhhs:
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; CHECK-NOFP16: // %bb.0: // %entry
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; CHECK-NOFP16-NEXT: fcvt s0, h0
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; CHECK-NOFP16-NEXT: frintx s0, s0
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; CHECK-NOFP16-NEXT: fcvtzs x0, s0
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; CHECK-NOFP16-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-NOFP16-NEXT: ret
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;
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; CHECK-FP16-LABEL: testmhhs:
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; CHECK-FP16: // %bb.0: // %entry
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; CHECK-FP16-NEXT: frintx h0, h0
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; CHECK-FP16-NEXT: fcvtzs x0, h0
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; CHECK-FP16-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-FP16-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
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%conv = trunc i64 %0 to i16
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ret i16 %conv
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}
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define i32 @testmhws(half %x) {
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; CHECK-NOFP16-LABEL: testmhws:
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; CHECK-NOFP16: // %bb.0: // %entry
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; CHECK-NOFP16-NEXT: fcvt s0, h0
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; CHECK-NOFP16-NEXT: frintx s0, s0
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; CHECK-NOFP16-NEXT: fcvtzs x0, s0
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; CHECK-NOFP16-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-NOFP16-NEXT: ret
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;
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; CHECK-FP16-LABEL: testmhws:
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; CHECK-FP16: // %bb.0: // %entry
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; CHECK-FP16-NEXT: frintx h0, h0
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; CHECK-FP16-NEXT: fcvtzs x0, h0
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; CHECK-FP16-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-FP16-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmhxs(half %x) {
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; CHECK-NOFP16-LABEL: testmhxs:
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; CHECK-NOFP16: // %bb.0: // %entry
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; CHECK-NOFP16-NEXT: fcvt s0, h0
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; CHECK-NOFP16-NEXT: frintx s0, s0
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; CHECK-NOFP16-NEXT: fcvtzs x0, s0
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; CHECK-NOFP16-NEXT: ret
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;
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; CHECK-FP16-LABEL: testmhxs:
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; CHECK-FP16: // %bb.0: // %entry
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; CHECK-FP16-NEXT: frintx h0, h0
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; CHECK-FP16-NEXT: fcvtzs x0, h0
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; CHECK-FP16-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
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ret i64 %0
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}
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declare i64 @llvm.llrint.i64.f16(half) nounwind readnone
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