d9a00ed366
This PR depends on https://github.com/llvm/llvm-project/pull/90264 In the current implementation, only leaf children of each internal node in the suffix tree are included as candidates for outlining. But all leaf descendants are outlining candidates, which we include in the new implementation. This is enabled on a flag `outliner-leaf-descendants` which is default to be true. The reason for _enabling this on a flag_ is because machine outliner is not the only pass that uses suffix tree. The reason for _having this default to be true_ is because including all leaf descendants show consistent size win. * For Clang/LLD, it shows around 3% reduction in text segment size when compared to the baseline `-Oz` linker binary. * For selected benchmark tests in LLVM test suite | run (CTMark/) | only leaf children | all leaf descendants | reduction % | |------------------|--------------------|----------------------|-------------| | lencod | 349624 | 348564 | -0.2004% | | SPASS | 219672 | 218440 | -0.4738% | | kc | 271956 | 250068 | -0.4506% | | sqlite3 | 223920 | 222484 | -0.5471% | | 7zip-benchmark | 405364 | 401244 | -0.3428% | | bullet | 139820 | 138340 | -0.8315% | | consumer-typeset | 295684 | 286628 | -1.2295% | | pairlocalalign | 72236 | 71936 | -0.2164% | | tramp3d-v4 | 189572 | 183676 | -2.9668% | This is part of an enhanced version of machine outliner -- see [RFC](https://discourse.llvm.org/t/rfc-enhanced-machine-outliner-part-1-fulllto-part-2-thinlto-nolto-to-come/78732).
170 lines
4.5 KiB
YAML
170 lines
4.5 KiB
YAML
# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs -frame-pointer=non-leaf -outliner-leaf-descendants=false %s -o - | FileCheck %s
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--- |
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@x = common global i32 0, align 4
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define void @baz() #0 {
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ret void
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}
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define i32 @main() #0 {
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ret i32 0
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}
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define void @bar(i32 %a) #0 {
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ret void
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}
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attributes #0 = { noinline noredzone }
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...
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---
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# This test ensures that we
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# - Create outlined functions
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# - Don't outline anything to do with LR or W30
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# - Save LR when it's not available
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# - Functions whose addresses are taken can still be outlined
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#
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# CHECK-LABEL: main
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# CHECK-LABEL: bb.1:
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# CHECK-DAG: BL @OUTLINED_FUNCTION_[[F0:[0-9]+]]
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# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG:[0-9]+]], 0
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# CHECK-NEXT: STRHHroW $w12, $x9, $w30, 1, 1
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# CHECK-NEXT: $lr = ORRXri $xzr, 1
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# CHECK-DAG: bb.2
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# CHECK: BL @OUTLINED_FUNCTION_[[F0]]
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# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0
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# CHECK-NEXT: STRHHroW $w12, $x9, $w30, 1, 1
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# CHECK-NEXT: $lr = ORRXri $xzr, 1
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# CHECK-DAG: bb.3
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# CHECK: BL @OUTLINED_FUNCTION_[[F0]]
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# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0
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# CHECK-NEXT: STRHHroW $w12, $x9, $w30, 1, 1
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# CHECK-NEXT: $lr = ORRXri $xzr, 1
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name: main
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $lr
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$sp = frame-setup SUBXri $sp, 16, 0
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renamable $x9 = ADRP target-flags(aarch64-page) @bar
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$x9 = ORRXri $xzr, 1
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$w12 = ORRWri $wzr, 1
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$w30 = ORRWri $wzr, 1
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$lr = ORRXri $xzr, 1
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bb.1:
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liveins: $lr
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$x20, $x19 = LDPXi $sp, 10
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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renamable $x9 = ADRP target-flags(aarch64-page) @x
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$x12 = ADDXri $sp, 48, 0;
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STRHHroW $w12, $x9, $w30, 1, 1
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$lr = ORRXri $xzr, 1
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bb.2:
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liveins: $lr
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$x20, $x19 = LDPXi $sp, 10
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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renamable $x9 = ADRP target-flags(aarch64-page) @x
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$x12 = ADDXri $sp, 48, 0;
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STRHHroW $w12, $x9, $w30, 1, 1
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$lr = ORRXri $xzr, 1
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bb.3:
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liveins: $lr
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$x20, $x19 = LDPXi $sp, 10
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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$w12 = ORRWri $wzr, 1
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renamable $x9 = ADRP target-flags(aarch64-page) @x
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$x12 = ADDXri $sp, 48, 0;
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STRHHroW $w12, $x9, $w30, 1, 1
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$lr = ORRXri $xzr, 1
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$sp = ADDXri $sp, 16, 0
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bb.4:
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liveins: $lr
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RET undef $lr
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...
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---
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# This test ensures that we can avoid saving LR when it's available.
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# It also makes sure that KILL instructions don't impact outlining.
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# CHECK-LABEL: bb.1:
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# CHECK-NOT: BL @baz, implicit-def dead $lr, implicit $sp
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# CHECK: BL @OUTLINED_FUNCTION_[[F1:[0-9]+]], implicit-def $lr, implicit $sp
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# CHECK-NEXT: $w11 = ORRWri $wzr, 2
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# CHECK-NEXT: BL @OUTLINED_FUNCTION_[[F1]], implicit-def $lr, implicit $sp
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# CHECK-NEXT: $w8 = ORRWri $wzr, 0
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# CHECK-NOT: $w11 = KILL renamable $w11, implicit killed $w11
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name: bar
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $lr, $w8
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$sp = frame-setup SUBXri $sp, 32, 0
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$fp = frame-setup ADDXri $sp, 16, 0
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bb.1:
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BL @baz, implicit-def dead $lr, implicit $sp
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$w11 = ORRWri $wzr, 1
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$w11 = ORRWri $wzr, 1
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$w11 = KILL renamable $w11, implicit killed $w11
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$w11 = ORRWri $wzr, 1
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$w11 = ORRWri $wzr, 1
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BL @baz, implicit-def dead $lr, implicit $sp
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$w11 = ORRWri $wzr, 1
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$w11 = ORRWri $wzr, 1
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$w11 = ORRWri $wzr, 2
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BL @baz, implicit-def dead $lr, implicit $sp
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$w11 = ORRWri $wzr, 1
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$w11 = ORRWri $wzr, 1
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$w11 = ORRWri $wzr, 1
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$w11 = ORRWri $wzr, 1
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BL @baz, implicit-def dead $lr, implicit $sp
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$w11 = ORRWri $wzr, 1
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$w11 = ORRWri $wzr, 1
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$w8 = ORRWri $wzr, 0
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bb.2:
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$w15 = ORRWri $wzr, 1
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$w15 = ORRWri $wzr, 1
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$w15 = ORRWri $wzr, 1
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$w15 = ORRWri $wzr, 1
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$x15 = ADDXri $sp, 48, 0;
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$w9 = ORRWri $wzr, 0
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$w15 = ORRWri $wzr, 1
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$w15 = ORRWri $wzr, 1
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$w15 = ORRWri $wzr, 1
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$w15 = ORRWri $wzr, 1
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$x15 = ADDXri $sp, 48, 0;
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$w8 = ORRWri $wzr, 0
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bb.3:
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$fp, $lr = LDPXi $sp, 2
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$sp = ADDXri $sp, 32, 0
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RET undef $lr
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...
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---
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name: baz
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $lr, $w8
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RET undef $lr
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# CHECK-LABEL: name: OUTLINED_FUNCTION_{{[0-9]}}
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# CHECK=LABEL: name: OUTLINED_FUNCTION_{{[1-9]}}
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