fe7fc54403
This adds a tablegen pattern to use ORRWrr (mov) as opposed to i64 AND 0xffffffff, as the mov will implicitly clear the upper bits. This can be seen as a zext(trunc(..)), and could be simpler if it is eliminated.
20 lines
596 B
LLVM
20 lines
596 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=0 | FileCheck %s
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define i32 @f(i64 %0) {
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; CHECK-LABEL: f:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #10 // =0xa
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; CHECK-NEXT: mov w9, w0
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; CHECK-NEXT: udiv x10, x9, x8
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; CHECK-NEXT: msub x0, x10, x8, x9
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; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-NEXT: ret
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%2 = trunc i64 %0 to i32
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%3 = freeze i32 %2
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%4 = zext i32 %3 to i64
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%5 = urem i64 %4, 10
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%6 = trunc i64 %5 to i32
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ret i32 %6
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}
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