a3cf8642bf
This patch tries to clean up some of the existing values in getMemOpInfo. All values should now be in bytes (not bits), and the MinOffset/MaxOffset are now always represented unscaled (the immediate that will be present in the final instruction). Although I could not find a place where it altered codegen, the offset of a post-index instruction will be 0, not scale*imm. A IsPostIndexLdStOpcode method has been added to try and make sure that case is handled properly.
64 lines
2.4 KiB
YAML
64 lines
2.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# Both the accesses should have an offset of 0
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# CHECK: Num BaseOps: 1, Offset: 0, OffsetIsScalable: 0, Width: LocationSize::precise(4)
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# CHECK: Num BaseOps: 1, Offset: 0, OffsetIsScalable: 0, Width: LocationSize::precise(4)
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
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target triple = "aarch64"
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define ptr @post(ptr %p, i32 %d1, i32 %d2) {
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entry:
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%d3 = mul i32 %d1, %d2
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%q = getelementptr i64, ptr %p, i64 3
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%r = getelementptr i64, ptr %p, i64 3
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store i32 %d3, ptr %p, align 8
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%0 = load i32, ptr %r, align 8
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store i32 %d1, ptr %p, align 8
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%add.ptr = getelementptr inbounds i8, ptr %p, i64 24
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ret ptr %add.ptr
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}
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...
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---
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name: post
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64common, preferred-register: '' }
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- { id: 1, class: gpr32, preferred-register: '' }
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- { id: 2, class: gpr32, preferred-register: '' }
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- { id: 3, class: gpr32, preferred-register: '' }
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- { id: 4, class: gpr64common, preferred-register: '' }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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- { reg: '$w1', virtual-reg: '%1' }
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- { reg: '$w2', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $x0, $w1, $w2
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; CHECK-LABEL: name: post
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; CHECK: liveins: $x0, $w1, $w2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY]], $wzr
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-NEXT: STRWui [[MADDWrrr]], [[COPY2]], 0 :: (store (s32) into %ir.p, align 8)
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; CHECK-NEXT: early-clobber [[COPY2]]:gpr64common = STRWpost [[COPY1]], [[COPY2]], 24 :: (store (s32) into %ir.p, align 8)
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; CHECK-NEXT: $x0 = COPY [[COPY2]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%2:gpr32 = COPY $w2
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%1:gpr32 = COPY $w1
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%4:gpr64common = COPY $x0
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%3:gpr32 = MADDWrrr %1, %2, $wzr
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STRWui %3, %4, 0 :: (store (s32) into %ir.p, align 8)
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early-clobber %4:gpr64common = STRWpost %1, %4, 24 :: (store (s32) into %ir.p, align 8)
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$x0 = COPY %4
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RET_ReallyLR implicit $x0
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...
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