19008d3218
Prior to this, fixed point multiplication would lead to this assertion
error on AArhc64, armv8, and armv7.
```
_Accum f(_Accum x, _Accum y) { return x * y; }
// ./bin/clang++ -ffixed-point /tmp/test2.cc -c -S -o - -target aarch64 -O3
clang++: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:10245: void llvm::TargetLowering::forceExpandWideMUL(SelectionDAG &, const SDLoc &, bool, EVT, const SDValue, const SDValue, const SDValue, const SDValue, SDValue &, SDValue &) const: Assertion `Ret.getOpcode() == ISD::MERGE_VALUES && "Ret value is a collection of constituent nodes holding result."' failed.
```
This path into forceExpandWideMUL should only be taken if we don't
support [US]MUL_LOHI or MULH[US] for the operand size (32 in this case).
But we should also check if we can just leverage regular wide
multiplication. That is, extend the operands from 32 to 64, do a regular
64-bit mul, then trunc and shift. These ops are certainly available on
aarch64 but for wider types.
207 lines
6.4 KiB
LLVM
207 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umull x8, w0, w1
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; CHECK-NEXT: lsr x9, x8, #32
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; CHECK-NEXT: extr w8, w9, w8, #2
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; CHECK-NEXT: cmp w9, #3
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; CHECK-NEXT: csinv w0, w8, wzr, ls
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; CHECK-NEXT: ret
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%tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 2)
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ret i32 %tmp
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: func2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul x8, x0, x1
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; CHECK-NEXT: umulh x9, x0, x1
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; CHECK-NEXT: extr x8, x9, x8, #2
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; CHECK-NEXT: cmp x9, #3
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; CHECK-NEXT: csinv x0, x8, xzr, ls
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; CHECK-NEXT: ret
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%tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 2)
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ret i64 %tmp
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; CHECK-LABEL: func3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #28
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; CHECK-NEXT: and w9, w1, #0xf
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; CHECK-NEXT: umull x8, w8, w9
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; CHECK-NEXT: lsr x9, x8, #32
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; CHECK-NEXT: extr w8, w9, w8, #2
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; CHECK-NEXT: cmp w9, #3
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; CHECK-NEXT: csinv w8, w8, wzr, ls
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; CHECK-NEXT: lsr w0, w8, #28
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; CHECK-NEXT: ret
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%tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 2)
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ret i4 %tmp
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}
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;; These result in regular integer multiplication with a saturation check.
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define i32 @func4(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umull x8, w0, w1
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; CHECK-NEXT: tst x8, #0xffffffff00000000
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; CHECK-NEXT: csinv w0, w8, wzr, eq
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; CHECK-NEXT: ret
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%tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 0)
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ret i32 %tmp
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}
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define i64 @func5(i64 %x, i64 %y) {
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; CHECK-LABEL: func5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umulh x8, x0, x1
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; CHECK-NEXT: mul x9, x0, x1
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; CHECK-NEXT: cmp xzr, x8
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; CHECK-NEXT: csinv x0, x9, xzr, eq
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; CHECK-NEXT: ret
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%tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 0)
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ret i64 %tmp
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}
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define i4 @func6(i4 %x, i4 %y) nounwind {
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; CHECK-LABEL: func6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #28
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; CHECK-NEXT: and w9, w1, #0xf
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; CHECK-NEXT: umull x8, w8, w9
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; CHECK-NEXT: tst x8, #0xffffffff00000000
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; CHECK-NEXT: csinv w8, w8, wzr, eq
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; CHECK-NEXT: lsr w0, w8, #28
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; CHECK-NEXT: ret
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%tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 0)
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ret i4 %tmp
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}
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define <2 x i32> @vec(<2 x i32> %x, <2 x i32> %y) nounwind {
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; CHECK-LABEL: vec:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov w8, v1.s[1]
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; CHECK-NEXT: mov w9, v0.s[1]
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; CHECK-NEXT: fmov w10, s0
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; CHECK-NEXT: umull x8, w9, w8
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; CHECK-NEXT: fmov w9, s1
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; CHECK-NEXT: umull x9, w10, w9
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; CHECK-NEXT: tst x8, #0xffffffff00000000
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; CHECK-NEXT: csinv w8, w8, wzr, eq
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; CHECK-NEXT: tst x9, #0xffffffff00000000
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; CHECK-NEXT: csinv w9, w9, wzr, eq
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; CHECK-NEXT: fmov s0, w9
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; CHECK-NEXT: mov v0.s[1], w8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%tmp = call <2 x i32> @llvm.umul.fix.sat.v2i32(<2 x i32> %x, <2 x i32> %y, i32 0)
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ret <2 x i32> %tmp
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}
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define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: vec2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, v1.s[1]
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; CHECK-NEXT: mov w9, v0.s[1]
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; CHECK-NEXT: fmov w10, s0
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; CHECK-NEXT: mov w11, v0.s[2]
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; CHECK-NEXT: mov w13, v0.s[3]
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; CHECK-NEXT: mov w12, v1.s[3]
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; CHECK-NEXT: umull x8, w9, w8
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; CHECK-NEXT: fmov w9, s1
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; CHECK-NEXT: umull x9, w10, w9
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; CHECK-NEXT: tst x8, #0xffffffff00000000
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; CHECK-NEXT: mov w10, v1.s[2]
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; CHECK-NEXT: csinv w8, w8, wzr, eq
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; CHECK-NEXT: tst x9, #0xffffffff00000000
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; CHECK-NEXT: csinv w9, w9, wzr, eq
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; CHECK-NEXT: fmov s0, w9
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; CHECK-NEXT: umull x9, w11, w10
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; CHECK-NEXT: mov v0.s[1], w8
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; CHECK-NEXT: tst x9, #0xffffffff00000000
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; CHECK-NEXT: csinv w8, w9, wzr, eq
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; CHECK-NEXT: umull x9, w13, w12
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; CHECK-NEXT: mov v0.s[2], w8
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; CHECK-NEXT: tst x9, #0xffffffff00000000
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; CHECK-NEXT: csinv w8, w9, wzr, eq
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; CHECK-NEXT: mov v0.s[3], w8
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; CHECK-NEXT: ret
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%tmp = call <4 x i32> @llvm.umul.fix.sat.v4i32(<4 x i32> %x, <4 x i32> %y, i32 0)
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ret <4 x i32> %tmp
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}
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define <4 x i64> @vec3(<4 x i64> %x, <4 x i64> %y) nounwind {
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; CHECK-LABEL: vec3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, v2.d[1]
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; CHECK-NEXT: mov x9, v0.d[1]
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; CHECK-NEXT: mov x14, v3.d[1]
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; CHECK-NEXT: mov x15, v1.d[1]
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; CHECK-NEXT: fmov x10, d2
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; CHECK-NEXT: fmov x11, d0
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; CHECK-NEXT: mul x12, x11, x10
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; CHECK-NEXT: mul x13, x9, x8
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; CHECK-NEXT: umulh x8, x9, x8
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; CHECK-NEXT: umulh x9, x11, x10
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; CHECK-NEXT: mul x10, x15, x14
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; CHECK-NEXT: extr x13, x8, x13, #32
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; CHECK-NEXT: umulh x11, x15, x14
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; CHECK-NEXT: fmov x14, d3
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; CHECK-NEXT: fmov x15, d1
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; CHECK-NEXT: mul x16, x15, x14
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; CHECK-NEXT: umulh x14, x15, x14
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; CHECK-NEXT: mov w15, #-1 // =0xffffffff
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; CHECK-NEXT: cmp x8, x15
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; CHECK-NEXT: extr x8, x9, x12, #32
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; CHECK-NEXT: csinv x12, x13, xzr, ls
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; CHECK-NEXT: cmp x9, x15
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; CHECK-NEXT: extr x9, x11, x10, #32
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; CHECK-NEXT: csinv x8, x8, xzr, ls
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; CHECK-NEXT: cmp x11, x15
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; CHECK-NEXT: csinv x9, x9, xzr, ls
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; CHECK-NEXT: fmov d0, x8
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; CHECK-NEXT: extr x10, x14, x16, #32
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; CHECK-NEXT: cmp x14, x15
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; CHECK-NEXT: csinv x10, x10, xzr, ls
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; CHECK-NEXT: mov v0.d[1], x12
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; CHECK-NEXT: fmov d1, x10
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; CHECK-NEXT: mov v1.d[1], x9
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; CHECK-NEXT: ret
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%tmp = call <4 x i64> @llvm.umul.fix.sat.v4i64(<4 x i64> %x, <4 x i64> %y, i32 32)
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ret <4 x i64> %tmp
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}
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define i64 @func7(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: func7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul x9, x0, x1
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; CHECK-NEXT: mov w8, #-1 // =0xffffffff
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; CHECK-NEXT: umulh x10, x0, x1
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; CHECK-NEXT: extr x9, x10, x9, #32
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; CHECK-NEXT: cmp x10, x8
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; CHECK-NEXT: csinv x0, x9, xzr, ls
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; CHECK-NEXT: ret
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%tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 32)
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ret i64 %tmp
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}
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define i64 @func8(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: func8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul x9, x0, x1
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; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
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; CHECK-NEXT: umulh x10, x0, x1
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; CHECK-NEXT: extr x9, x10, x9, #63
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; CHECK-NEXT: cmp x10, x8
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; CHECK-NEXT: csinv x0, x9, xzr, ls
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; CHECK-NEXT: ret
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%tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 63)
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ret i64 %tmp
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}
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