9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
72 lines
1.8 KiB
YAML
72 lines
1.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
|
|
|
---
|
|
|
|
name: ffbl_b32_s32_s_s
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
|
|
; CHECK-LABEL: name: ffbl_b32_s32_s_s
|
|
; CHECK: liveins: $sgpr0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; CHECK-NEXT: [[S_FF1_I32_B32_:%[0-9]+]]:sreg_32 = S_FF1_I32_B32 [[COPY]]
|
|
; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FF1_I32_B32_]]
|
|
%0:sgpr(s32) = COPY $sgpr0
|
|
%1:sgpr(s32) = G_AMDGPU_FFBL_B32 %0
|
|
S_ENDPGM 0, implicit %1
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: ffbl_b32_s32_v_v
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: ffbl_b32_s32_v_v
|
|
; CHECK: liveins: $vgpr0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; CHECK-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
|
|
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:vgpr(s32) = G_AMDGPU_FFBL_B32 %0
|
|
S_ENDPGM 0, implicit %1
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: ffbl_b32_v_s
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
|
|
; CHECK-LABEL: name: ffbl_b32_v_s
|
|
; CHECK: liveins: $sgpr0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; CHECK-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
|
|
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
|
|
%0:sgpr(s32) = COPY $sgpr0
|
|
%1:vgpr(s32) = G_AMDGPU_FFBL_B32 %0
|
|
S_ENDPGM 0, implicit %1
|
|
|
|
...
|