92663defb1
- `llvm/test/CodeGen/AMDGPU/andorbitset.ll` - `llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll` - `llvm/test/CodeGen/AMDGPU/fabs.f64.ll` - `llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll` - `llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll`
105 lines
3.4 KiB
LLVM
105 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=tahiti -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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define amdgpu_kernel void @s_or_to_orn2(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_or_to_orn2:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s4, s[2:3], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_orn2_b32 s4, s4, 50
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = or i32 %in, -51
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_or_to_orn2_imm0(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_or_to_orn2_imm0:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s4, s[2:3], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_orn2_b32 s4, s4, 50
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = or i32 -51, %in
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_and_to_andn2(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_and_to_andn2:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s4, s[2:3], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_andn2_b32 s4, s4, 50
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = and i32 %in, -51
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_and_to_andn2_imm0(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_and_to_andn2_imm0:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s4, s[2:3], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_andn2_b32 s4, s4, 50
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = and i32 -51, %in
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_xor_to_xnor(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_xor_to_xnor:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s4, s[2:3], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_xnor_b32 s4, s4, 50
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = xor i32 %in, -51
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_xor_to_xnor_imm0(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_xor_to_xnor_imm0:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s4, s[2:3], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_xnor_b32 s4, s4, 50
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = xor i32 -51, %in
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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