f3a02253e9
It is documented that immarg is only valid on intrinsic declarations, although the verifier also tolerates it on intrinsic calls. This patch updates tests that are not specifically testing the behavior of the IR parser or verifier.
43 lines
1.6 KiB
LLVM
43 lines
1.6 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs | FileCheck %s
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; Check that the redundant immediate MOV instruction
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; (by-product of handling phi nodes) is not found
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; in the generated code.
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; CHECK-LABEL: {{^}}mov_opt:
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; CHECK: s_mov_b32 [[SREG:s[0-9]+]], 1.0
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; CHECK: %bb.1:
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; CHECK-NOT: v_mov_b32_e32 {{v[0-9]+}}, 1.0
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; CHECK: BB0_3:
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; CHECK: v_mov_b32_e32 v{{[0-9]+}}, [[SREG]]
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define amdgpu_ps void @mov_opt(i32 %arg, i32 inreg %arg1, i32 inreg %arg2) local_unnamed_addr #0 {
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bb:
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%tmp = icmp eq i32 %arg1, 0
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br i1 %tmp, label %bb3, label %bb10
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bb3: ; preds = %bb
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%tmp4 = icmp eq i32 %arg2, 0
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br i1 %tmp4, label %bb5, label %bb10
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bb5: ; preds = %bb3
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%tmp6 = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(6) null, i32 0, i32 0, i32 %arg
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%tmp7 = load i32, ptr addrspace(6) %tmp6
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%tmp8 = icmp eq i32 %tmp7, 1
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br i1 %tmp8, label %bb10, label %bb9
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bb9: ; preds = %bb5
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br label %bb10
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bb10: ; preds = %bb9, %bb5, %bb3, %bb
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%tmp11 = phi float [ 1.000000e+00, %bb3 ], [ 0.000000e+00, %bb9 ], [ 1.000000e+00, %bb ], [ undef, %bb5 ]
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call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %tmp11, float undef, float undef, float undef, i1 false, i1 false) #0
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ret void
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}
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; Function Attrs: inaccessiblememonly nounwind
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declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #1
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attributes #0 = { nounwind }
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attributes #1 = { inaccessiblememonly nounwind }
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