33e6b488be
The load narrowing part of TargetLowering::SimplifySetCC is updated according to this: 1) The offset calculation (for big endian) did not work properly for non byte-sized types. This is basically solved by an early exit if the memory type isn't byte-sized. But the code is also corrected to use the store size when calculating the offset. 2) To still allow some optimizations for non-byte-sized types the TargetLowering::isPaddedAtMostSignificantBitsWhenStored hook is added. By default it assumes that scalar integer types are padded starting at the most significant bits, if the type needs padding when being stored to memory. 3) Allow optimizing when isPaddedAtMostSignificantBitsWhenStored is true, as that hook makes it possible for TargetLowering to know how the non byte-sized value is aligned in memory. 4) Update the algorithm to always search for a narrowed load with a power-of-2 byte-sized type. In the past the algorithm started with the the width of the original load, and then divided it by two for each iteration. But for a type such as i48 that would just end up trying to narrow the load into a i24 or i12 load, and then we would fail sooner or later due to not finding a newVT that fulfilled newVT.isRound(). With this new approach we can narrow the i48 load into either an i8, i16 or i32 load. By checking if such a load is allowed (e.g. alignment wise) for any "multiple of 8 offset", then we can find more opportunities for the optimization to trigger. So even for a byte-sized type such as i32 we may now end up narrowing the load into loading the 16 bits starting at offset 8 (if that is allowed by the target). The old algorithm did not even consider that case. 5) Also start using getObjectPtrOffset instead of getMemBasePlusOffset when creating the new ptr. This way we get "nsw" on the add.
665 lines
19 KiB
LLVM
665 lines
19 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -O1 -mtriple arm -o - %s | FileCheck --check-prefix CHECK-LE %s
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; RUN: llc -O1 -mtriple armv7 -o - %s | FileCheck --check-prefix CHECK-V7-LE %s
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; RUN: llc -O1 -mtriple armeb -o - %s | FileCheck --check-prefix CHECK-BE %s
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; RUN: llc -O1 -mtriple armv7eb -o - %s | FileCheck --check-prefix CHECK-V7-BE %s
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; A collection of regression tests to verify the load-narrowing part of
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; TargetLowering::SimplifySetCC (and/or other similar rewrites such as
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; combining AND+LOAD into ZEXTLOAD).
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;
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; Using both arm and armv7 to show that alignment restrictions are
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; considered for the narrowed load (armv7 is a bit more relaxed when it
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; comes to unaligned memory accesses).
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;--------------------------------------------------------------------------
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; Test non byte-sized types.
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;
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; As long as LLVM IR isn't defining where the padding goes we can't really
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; optimize these (without adding a target lowering hook that can inform
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; ISel about which bits are padding).
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; --------------------------------------------------------------------------
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define i1 @test_129_15_0(ptr %y) {
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; CHECK-LE-LABEL: test_129_15_0:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldrh r0, [r0]
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; CHECK-LE-NEXT: mov r1, #255
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; CHECK-LE-NEXT: orr r1, r1, #32512
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; CHECK-LE-NEXT: ands r0, r0, r1
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; CHECK-LE-NEXT: movne r0, #1
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_129_15_0:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldrh r0, [r0]
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; CHECK-V7-LE-NEXT: bfc r0, #15, #17
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; CHECK-V7-LE-NEXT: cmp r0, #0
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; CHECK-V7-LE-NEXT: movwne r0, #1
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_129_15_0:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldr r1, [r0, #12]
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; CHECK-BE-NEXT: ldrb r0, [r0, #16]
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; CHECK-BE-NEXT: orr r0, r0, r1, lsl #8
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; CHECK-BE-NEXT: mov r1, #255
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; CHECK-BE-NEXT: orr r1, r1, #32512
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; CHECK-BE-NEXT: ands r0, r0, r1
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; CHECK-BE-NEXT: movne r0, #1
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; CHECK-BE-NEXT: mov pc, lr
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;
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; CHECK-V7-BE-LABEL: test_129_15_0:
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; CHECK-V7-BE: @ %bb.0:
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; CHECK-V7-BE-NEXT: ldrh r0, [r0, #15]
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; CHECK-V7-BE-NEXT: bfc r0, #15, #17
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; CHECK-V7-BE-NEXT: cmp r0, #0
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; CHECK-V7-BE-NEXT: movwne r0, #1
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; CHECK-V7-BE-NEXT: bx lr
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%a = load i129, ptr %y
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%b = and i129 %a, u0x7fff
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%cmp = icmp ne i129 %b, 0
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ret i1 %cmp
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}
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define i1 @test_126_20_4(ptr %y) {
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; CHECK-LE-LABEL: test_126_20_4:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldr r0, [r0]
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; CHECK-LE-NEXT: mvn r1, #15
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; CHECK-LE-NEXT: sub r1, r1, #-16777216
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; CHECK-LE-NEXT: ands r0, r0, r1
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; CHECK-LE-NEXT: movne r0, #1
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_126_20_4:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldr r0, [r0]
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; CHECK-V7-LE-NEXT: movw r1, #65520
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; CHECK-V7-LE-NEXT: movt r1, #255
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; CHECK-V7-LE-NEXT: ands r0, r0, r1
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; CHECK-V7-LE-NEXT: movwne r0, #1
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_126_20_4:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldr r0, [r0, #12]
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; CHECK-BE-NEXT: mvn r1, #15
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; CHECK-BE-NEXT: sub r1, r1, #-16777216
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; CHECK-BE-NEXT: ands r0, r0, r1
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; CHECK-BE-NEXT: movne r0, #1
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; CHECK-BE-NEXT: mov pc, lr
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;
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; CHECK-V7-BE-LABEL: test_126_20_4:
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; CHECK-V7-BE: @ %bb.0:
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; CHECK-V7-BE-NEXT: ldr r0, [r0, #12]
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; CHECK-V7-BE-NEXT: movw r1, #65520
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; CHECK-V7-BE-NEXT: movt r1, #255
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; CHECK-V7-BE-NEXT: ands r0, r0, r1
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; CHECK-V7-BE-NEXT: movwne r0, #1
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; CHECK-V7-BE-NEXT: bx lr
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%a = load i126, ptr %y
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%b = and i126 %a, u0xfffff0
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%cmp = icmp ne i126 %b, 0
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ret i1 %cmp
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}
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define i1 @test_33_8_0(ptr %y) {
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; CHECK-LE-LABEL: test_33_8_0:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldrb r0, [r0]
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; CHECK-LE-NEXT: cmp r0, #0
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; CHECK-LE-NEXT: movne r0, #1
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_33_8_0:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldrb r0, [r0]
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; CHECK-V7-LE-NEXT: cmp r0, #0
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; CHECK-V7-LE-NEXT: movwne r0, #1
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_33_8_0:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldrb r0, [r0, #4]
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; CHECK-BE-NEXT: cmp r0, #0
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; CHECK-BE-NEXT: movne r0, #1
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; CHECK-BE-NEXT: mov pc, lr
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;
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; CHECK-V7-BE-LABEL: test_33_8_0:
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; CHECK-V7-BE: @ %bb.0:
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; CHECK-V7-BE-NEXT: ldrb r0, [r0, #4]
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; CHECK-V7-BE-NEXT: cmp r0, #0
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; CHECK-V7-BE-NEXT: movwne r0, #1
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; CHECK-V7-BE-NEXT: bx lr
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%a = load i33, ptr %y
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%b = and i33 %a, u0xff
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%cmp = icmp ne i33 %b, 0
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ret i1 %cmp
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}
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define i1 @test_33_1_32(ptr %y) {
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; CHECK-LE-LABEL: test_33_1_32:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldrb r0, [r0, #4]
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_33_1_32:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldrb r0, [r0, #4]
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_33_1_32:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldr r0, [r0]
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; CHECK-BE-NEXT: lsr r0, r0, #24
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; CHECK-BE-NEXT: mov pc, lr
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;
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; CHECK-V7-BE-LABEL: test_33_1_32:
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; CHECK-V7-BE: @ %bb.0:
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; CHECK-V7-BE-NEXT: ldr r0, [r0]
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; CHECK-V7-BE-NEXT: lsr r0, r0, #24
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; CHECK-V7-BE-NEXT: bx lr
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%a = load i33, ptr %y
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%b = and i33 %a, u0x100000000
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%cmp = icmp ne i33 %b, 0
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ret i1 %cmp
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}
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define i1 @test_33_1_31(ptr %y) {
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; CHECK-LE-LABEL: test_33_1_31:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldrb r0, [r0, #3]
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; CHECK-LE-NEXT: lsr r0, r0, #7
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_33_1_31:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldrb r0, [r0, #3]
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; CHECK-V7-LE-NEXT: lsr r0, r0, #7
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_33_1_31:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldrb r0, [r0, #1]
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; CHECK-BE-NEXT: lsr r0, r0, #7
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; CHECK-BE-NEXT: mov pc, lr
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;
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; CHECK-V7-BE-LABEL: test_33_1_31:
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; CHECK-V7-BE: @ %bb.0:
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; CHECK-V7-BE-NEXT: ldrb r0, [r0, #1]
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; CHECK-V7-BE-NEXT: lsr r0, r0, #7
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; CHECK-V7-BE-NEXT: bx lr
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%a = load i33, ptr %y
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%b = and i33 %a, u0x80000000
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%cmp = icmp ne i33 %b, 0
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ret i1 %cmp
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}
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define i1 @test_33_1_0(ptr %y) {
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; CHECK-LE-LABEL: test_33_1_0:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldrb r0, [r0]
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; CHECK-LE-NEXT: and r0, r0, #1
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_33_1_0:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldrb r0, [r0]
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; CHECK-V7-LE-NEXT: and r0, r0, #1
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_33_1_0:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldrb r0, [r0, #4]
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; CHECK-BE-NEXT: and r0, r0, #1
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; CHECK-BE-NEXT: mov pc, lr
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;
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; CHECK-V7-BE-LABEL: test_33_1_0:
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; CHECK-V7-BE: @ %bb.0:
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; CHECK-V7-BE-NEXT: ldrb r0, [r0, #4]
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; CHECK-V7-BE-NEXT: and r0, r0, #1
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; CHECK-V7-BE-NEXT: bx lr
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%a = load i33, ptr %y
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%b = and i33 %a, u0x1
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%cmp = icmp ne i33 %b, 0
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ret i1 %cmp
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}
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;--------------------------------------------------------------------------
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; Test byte-sized types.
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;--------------------------------------------------------------------------
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define i1 @test_128_20_4(ptr %y) {
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; CHECK-LE-LABEL: test_128_20_4:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldr r0, [r0]
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; CHECK-LE-NEXT: mvn r1, #15
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; CHECK-LE-NEXT: sub r1, r1, #-16777216
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; CHECK-LE-NEXT: ands r0, r0, r1
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; CHECK-LE-NEXT: movne r0, #1
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_128_20_4:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldr r0, [r0]
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; CHECK-V7-LE-NEXT: movw r1, #65520
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; CHECK-V7-LE-NEXT: movt r1, #255
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; CHECK-V7-LE-NEXT: ands r0, r0, r1
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; CHECK-V7-LE-NEXT: movwne r0, #1
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_128_20_4:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldr r0, [r0, #12]
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; CHECK-BE-NEXT: mvn r1, #15
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; CHECK-BE-NEXT: sub r1, r1, #-16777216
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; CHECK-BE-NEXT: ands r0, r0, r1
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; CHECK-BE-NEXT: movne r0, #1
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; CHECK-BE-NEXT: mov pc, lr
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;
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; CHECK-V7-BE-LABEL: test_128_20_4:
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; CHECK-V7-BE: @ %bb.0:
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; CHECK-V7-BE-NEXT: ldr r0, [r0, #12]
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; CHECK-V7-BE-NEXT: movw r1, #65520
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; CHECK-V7-BE-NEXT: movt r1, #255
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; CHECK-V7-BE-NEXT: ands r0, r0, r1
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; CHECK-V7-BE-NEXT: movwne r0, #1
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; CHECK-V7-BE-NEXT: bx lr
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%a = load i128, ptr %y
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%b = and i128 %a, u0xfffff0
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%cmp = icmp ne i128 %b, 0
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ret i1 %cmp
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}
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define i1 @test_48_16_0(ptr %y) {
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; CHECK-LE-LABEL: test_48_16_0:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldrh r0, [r0]
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; CHECK-LE-NEXT: cmp r0, #0
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; CHECK-LE-NEXT: movne r0, #1
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_48_16_0:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldrh r0, [r0]
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; CHECK-V7-LE-NEXT: cmp r0, #0
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; CHECK-V7-LE-NEXT: movwne r0, #1
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_48_16_0:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldrh r0, [r0, #4]
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; CHECK-BE-NEXT: cmp r0, #0
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; CHECK-BE-NEXT: movne r0, #1
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; CHECK-BE-NEXT: mov pc, lr
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;
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; CHECK-V7-BE-LABEL: test_48_16_0:
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; CHECK-V7-BE: @ %bb.0:
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; CHECK-V7-BE-NEXT: ldrh r0, [r0, #4]
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; CHECK-V7-BE-NEXT: cmp r0, #0
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; CHECK-V7-BE-NEXT: movwne r0, #1
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; CHECK-V7-BE-NEXT: bx lr
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%a = load i48, ptr %y
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%b = and i48 %a, u0xffff
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%cmp = icmp ne i48 %b, 0
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ret i1 %cmp
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}
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define i1 @test_48_16_8(ptr %y) {
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; CHECK-LE-LABEL: test_48_16_8:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldrh r0, [r0, #1]
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; CHECK-LE-NEXT: lsls r0, r0, #8
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; CHECK-LE-NEXT: movne r0, #1
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_48_16_8:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldrh r0, [r0, #1]
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; CHECK-V7-LE-NEXT: cmp r0, #0
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; CHECK-V7-LE-NEXT: movwne r0, #1
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_48_16_8:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldrh r0, [r0, #3]
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; CHECK-BE-NEXT: cmp r0, #0
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; CHECK-BE-NEXT: movne r0, #1
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; CHECK-BE-NEXT: mov pc, lr
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;
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; CHECK-V7-BE-LABEL: test_48_16_8:
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; CHECK-V7-BE: @ %bb.0:
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; CHECK-V7-BE-NEXT: ldrh r0, [r0, #3]
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; CHECK-V7-BE-NEXT: cmp r0, #0
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; CHECK-V7-BE-NEXT: movwne r0, #1
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; CHECK-V7-BE-NEXT: bx lr
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%a = load i48, ptr %y
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%b = and i48 %a, u0xffff00
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%cmp = icmp ne i48 %b, 0
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ret i1 %cmp
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}
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define i1 @test_48_16_16(ptr %y) {
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; CHECK-LE-LABEL: test_48_16_16:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: ldrh r0, [r0, #2]
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; CHECK-LE-NEXT: cmp r0, #0
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; CHECK-LE-NEXT: movne r0, #1
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-V7-LE-LABEL: test_48_16_16:
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; CHECK-V7-LE: @ %bb.0:
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; CHECK-V7-LE-NEXT: ldrh r0, [r0, #2]
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; CHECK-V7-LE-NEXT: cmp r0, #0
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; CHECK-V7-LE-NEXT: movwne r0, #1
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; CHECK-V7-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_48_16_16:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: ldrh r0, [r0, #2]
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; CHECK-BE-NEXT: cmp r0, #0
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; CHECK-BE-NEXT: movne r0, #1
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; CHECK-BE-NEXT: mov pc, lr
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;
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|
; CHECK-V7-BE-LABEL: test_48_16_16:
|
|
; CHECK-V7-BE: @ %bb.0:
|
|
; CHECK-V7-BE-NEXT: ldrh r0, [r0, #2]
|
|
; CHECK-V7-BE-NEXT: cmp r0, #0
|
|
; CHECK-V7-BE-NEXT: movwne r0, #1
|
|
; CHECK-V7-BE-NEXT: bx lr
|
|
%a = load i48, ptr %y
|
|
%b = and i48 %a, u0xffff0000
|
|
%cmp = icmp ne i48 %b, 0
|
|
ret i1 %cmp
|
|
}
|
|
|
|
define i1 @test_48_16_32(ptr %y) {
|
|
; CHECK-LE-LABEL: test_48_16_32:
|
|
; CHECK-LE: @ %bb.0:
|
|
; CHECK-LE-NEXT: ldrh r0, [r0, #4]
|
|
; CHECK-LE-NEXT: cmp r0, #0
|
|
; CHECK-LE-NEXT: movne r0, #1
|
|
; CHECK-LE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-LE-LABEL: test_48_16_32:
|
|
; CHECK-V7-LE: @ %bb.0:
|
|
; CHECK-V7-LE-NEXT: ldrh r0, [r0, #4]
|
|
; CHECK-V7-LE-NEXT: cmp r0, #0
|
|
; CHECK-V7-LE-NEXT: movwne r0, #1
|
|
; CHECK-V7-LE-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_48_16_32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: ldrh r0, [r0]
|
|
; CHECK-BE-NEXT: cmp r0, #0
|
|
; CHECK-BE-NEXT: movne r0, #1
|
|
; CHECK-BE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-BE-LABEL: test_48_16_32:
|
|
; CHECK-V7-BE: @ %bb.0:
|
|
; CHECK-V7-BE-NEXT: ldrh r0, [r0]
|
|
; CHECK-V7-BE-NEXT: cmp r0, #0
|
|
; CHECK-V7-BE-NEXT: movwne r0, #1
|
|
; CHECK-V7-BE-NEXT: bx lr
|
|
%a = load i48, ptr %y
|
|
%b = and i48 %a, u0xffff00000000
|
|
%cmp = icmp ne i48 %b, 0
|
|
ret i1 %cmp
|
|
}
|
|
|
|
define i1 @test_48_17_0(ptr %y) {
|
|
; CHECK-LE-LABEL: test_48_17_0:
|
|
; CHECK-LE: @ %bb.0:
|
|
; CHECK-LE-NEXT: ldr r0, [r0]
|
|
; CHECK-LE-NEXT: ldr r1, .LCPI11_0
|
|
; CHECK-LE-NEXT: ands r0, r0, r1
|
|
; CHECK-LE-NEXT: movne r0, #1
|
|
; CHECK-LE-NEXT: mov pc, lr
|
|
; CHECK-LE-NEXT: .p2align 2
|
|
; CHECK-LE-NEXT: @ %bb.1:
|
|
; CHECK-LE-NEXT: .LCPI11_0:
|
|
; CHECK-LE-NEXT: .long 131071 @ 0x1ffff
|
|
;
|
|
; CHECK-V7-LE-LABEL: test_48_17_0:
|
|
; CHECK-V7-LE: @ %bb.0:
|
|
; CHECK-V7-LE-NEXT: ldr r0, [r0]
|
|
; CHECK-V7-LE-NEXT: bfc r0, #17, #15
|
|
; CHECK-V7-LE-NEXT: cmp r0, #0
|
|
; CHECK-V7-LE-NEXT: movwne r0, #1
|
|
; CHECK-V7-LE-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_48_17_0:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: ldr r1, [r0]
|
|
; CHECK-BE-NEXT: ldrh r0, [r0, #4]
|
|
; CHECK-BE-NEXT: orr r0, r0, r1, lsl #16
|
|
; CHECK-BE-NEXT: ldr r1, .LCPI11_0
|
|
; CHECK-BE-NEXT: ands r0, r0, r1
|
|
; CHECK-BE-NEXT: movne r0, #1
|
|
; CHECK-BE-NEXT: mov pc, lr
|
|
; CHECK-BE-NEXT: .p2align 2
|
|
; CHECK-BE-NEXT: @ %bb.1:
|
|
; CHECK-BE-NEXT: .LCPI11_0:
|
|
; CHECK-BE-NEXT: .long 131071 @ 0x1ffff
|
|
;
|
|
; CHECK-V7-BE-LABEL: test_48_17_0:
|
|
; CHECK-V7-BE: @ %bb.0:
|
|
; CHECK-V7-BE-NEXT: ldr r0, [r0, #2]
|
|
; CHECK-V7-BE-NEXT: bfc r0, #17, #15
|
|
; CHECK-V7-BE-NEXT: cmp r0, #0
|
|
; CHECK-V7-BE-NEXT: movwne r0, #1
|
|
; CHECK-V7-BE-NEXT: bx lr
|
|
%a = load i48, ptr %y
|
|
%b = and i48 %a, u0x1ffff
|
|
%cmp = icmp ne i48 %b, 0
|
|
ret i1 %cmp
|
|
}
|
|
|
|
define i1 @test_40_16_0(ptr %y) {
|
|
; CHECK-LE-LABEL: test_40_16_0:
|
|
; CHECK-LE: @ %bb.0:
|
|
; CHECK-LE-NEXT: ldrh r0, [r0]
|
|
; CHECK-LE-NEXT: cmp r0, #0
|
|
; CHECK-LE-NEXT: movne r0, #1
|
|
; CHECK-LE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-LE-LABEL: test_40_16_0:
|
|
; CHECK-V7-LE: @ %bb.0:
|
|
; CHECK-V7-LE-NEXT: ldrh r0, [r0]
|
|
; CHECK-V7-LE-NEXT: cmp r0, #0
|
|
; CHECK-V7-LE-NEXT: movwne r0, #1
|
|
; CHECK-V7-LE-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_40_16_0:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: ldrh r0, [r0, #3]
|
|
; CHECK-BE-NEXT: cmp r0, #0
|
|
; CHECK-BE-NEXT: movne r0, #1
|
|
; CHECK-BE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-BE-LABEL: test_40_16_0:
|
|
; CHECK-V7-BE: @ %bb.0:
|
|
; CHECK-V7-BE-NEXT: ldrh r0, [r0, #3]
|
|
; CHECK-V7-BE-NEXT: cmp r0, #0
|
|
; CHECK-V7-BE-NEXT: movwne r0, #1
|
|
; CHECK-V7-BE-NEXT: bx lr
|
|
%a = load i40, ptr %y
|
|
%b = and i40 %a, u0xffff
|
|
%cmp = icmp ne i40 %b, 0
|
|
ret i1 %cmp
|
|
}
|
|
|
|
define i1 @test_40_1_32(ptr %y) {
|
|
; CHECK-LE-LABEL: test_40_1_32:
|
|
; CHECK-LE: @ %bb.0:
|
|
; CHECK-LE-NEXT: ldrb r0, [r0, #4]
|
|
; CHECK-LE-NEXT: and r0, r0, #1
|
|
; CHECK-LE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-LE-LABEL: test_40_1_32:
|
|
; CHECK-V7-LE: @ %bb.0:
|
|
; CHECK-V7-LE-NEXT: ldrb r0, [r0, #4]
|
|
; CHECK-V7-LE-NEXT: and r0, r0, #1
|
|
; CHECK-V7-LE-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_40_1_32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: ldrb r0, [r0]
|
|
; CHECK-BE-NEXT: and r0, r0, #1
|
|
; CHECK-BE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-BE-LABEL: test_40_1_32:
|
|
; CHECK-V7-BE: @ %bb.0:
|
|
; CHECK-V7-BE-NEXT: ldrb r0, [r0]
|
|
; CHECK-V7-BE-NEXT: and r0, r0, #1
|
|
; CHECK-V7-BE-NEXT: bx lr
|
|
%a = load i40, ptr %y
|
|
%b = and i40 %a, u0x100000000
|
|
%cmp = icmp ne i40 %b, 0
|
|
ret i1 %cmp
|
|
}
|
|
|
|
define i1 @test_24_16_0(ptr %y) {
|
|
; CHECK-LE-LABEL: test_24_16_0:
|
|
; CHECK-LE: @ %bb.0:
|
|
; CHECK-LE-NEXT: ldrh r0, [r0]
|
|
; CHECK-LE-NEXT: cmp r0, #0
|
|
; CHECK-LE-NEXT: movne r0, #1
|
|
; CHECK-LE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-LE-LABEL: test_24_16_0:
|
|
; CHECK-V7-LE: @ %bb.0:
|
|
; CHECK-V7-LE-NEXT: ldrh r0, [r0]
|
|
; CHECK-V7-LE-NEXT: cmp r0, #0
|
|
; CHECK-V7-LE-NEXT: movwne r0, #1
|
|
; CHECK-V7-LE-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_24_16_0:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: ldrh r0, [r0, #1]
|
|
; CHECK-BE-NEXT: cmp r0, #0
|
|
; CHECK-BE-NEXT: movne r0, #1
|
|
; CHECK-BE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-BE-LABEL: test_24_16_0:
|
|
; CHECK-V7-BE: @ %bb.0:
|
|
; CHECK-V7-BE-NEXT: ldrh r0, [r0, #1]
|
|
; CHECK-V7-BE-NEXT: cmp r0, #0
|
|
; CHECK-V7-BE-NEXT: movwne r0, #1
|
|
; CHECK-V7-BE-NEXT: bx lr
|
|
%a = load i24, ptr %y
|
|
%b = and i24 %a, u0xffff
|
|
%cmp = icmp ne i24 %b, 0
|
|
ret i1 %cmp
|
|
}
|
|
|
|
define i1 @test_24_8_8(ptr %y) {
|
|
; CHECK-LE-LABEL: test_24_8_8:
|
|
; CHECK-LE: @ %bb.0:
|
|
; CHECK-LE-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-LE-NEXT: lsls r0, r0, #8
|
|
; CHECK-LE-NEXT: movne r0, #1
|
|
; CHECK-LE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-LE-LABEL: test_24_8_8:
|
|
; CHECK-V7-LE: @ %bb.0:
|
|
; CHECK-V7-LE-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-V7-LE-NEXT: lsls r0, r0, #8
|
|
; CHECK-V7-LE-NEXT: movwne r0, #1
|
|
; CHECK-V7-LE-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_24_8_8:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-BE-NEXT: lsls r0, r0, #8
|
|
; CHECK-BE-NEXT: movne r0, #1
|
|
; CHECK-BE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-BE-LABEL: test_24_8_8:
|
|
; CHECK-V7-BE: @ %bb.0:
|
|
; CHECK-V7-BE-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-V7-BE-NEXT: lsls r0, r0, #8
|
|
; CHECK-V7-BE-NEXT: movwne r0, #1
|
|
; CHECK-V7-BE-NEXT: bx lr
|
|
%a = load i24, ptr %y
|
|
%b = and i24 %a, u0xff00
|
|
%cmp = icmp ne i24 %b, 0
|
|
ret i1 %cmp
|
|
}
|
|
|
|
define i1 @test_24_8_12(ptr %y) {
|
|
; CHECK-LE-LABEL: test_24_8_12:
|
|
; CHECK-LE: @ %bb.0:
|
|
; CHECK-LE-NEXT: ldrb r1, [r0, #2]
|
|
; CHECK-LE-NEXT: ldrh r0, [r0]
|
|
; CHECK-LE-NEXT: orr r0, r0, r1, lsl #16
|
|
; CHECK-LE-NEXT: ands r0, r0, #1044480
|
|
; CHECK-LE-NEXT: movne r0, #1
|
|
; CHECK-LE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-LE-LABEL: test_24_8_12:
|
|
; CHECK-V7-LE: @ %bb.0:
|
|
; CHECK-V7-LE-NEXT: ldrb r1, [r0, #2]
|
|
; CHECK-V7-LE-NEXT: ldrh r0, [r0]
|
|
; CHECK-V7-LE-NEXT: orr r0, r0, r1, lsl #16
|
|
; CHECK-V7-LE-NEXT: ands r0, r0, #1044480
|
|
; CHECK-V7-LE-NEXT: movwne r0, #1
|
|
; CHECK-V7-LE-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_24_8_12:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: ldrh r0, [r0]
|
|
; CHECK-BE-NEXT: mov r1, #1044480
|
|
; CHECK-BE-NEXT: ands r0, r1, r0, lsl #8
|
|
; CHECK-BE-NEXT: movne r0, #1
|
|
; CHECK-BE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-BE-LABEL: test_24_8_12:
|
|
; CHECK-V7-BE: @ %bb.0:
|
|
; CHECK-V7-BE-NEXT: ldrh r0, [r0]
|
|
; CHECK-V7-BE-NEXT: mov r1, #1044480
|
|
; CHECK-V7-BE-NEXT: ands r0, r1, r0, lsl #8
|
|
; CHECK-V7-BE-NEXT: movwne r0, #1
|
|
; CHECK-V7-BE-NEXT: bx lr
|
|
%a = load i24, ptr %y
|
|
%b = and i24 %a, u0xff000
|
|
%cmp = icmp ne i24 %b, 0
|
|
ret i1 %cmp
|
|
}
|
|
|
|
define i1 @test_24_8_16(ptr %y) {
|
|
; CHECK-LE-LABEL: test_24_8_16:
|
|
; CHECK-LE: @ %bb.0:
|
|
; CHECK-LE-NEXT: ldrb r0, [r0, #2]
|
|
; CHECK-LE-NEXT: lsls r0, r0, #16
|
|
; CHECK-LE-NEXT: movne r0, #1
|
|
; CHECK-LE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-LE-LABEL: test_24_8_16:
|
|
; CHECK-V7-LE: @ %bb.0:
|
|
; CHECK-V7-LE-NEXT: ldrb r0, [r0, #2]
|
|
; CHECK-V7-LE-NEXT: lsls r0, r0, #16
|
|
; CHECK-V7-LE-NEXT: movwne r0, #1
|
|
; CHECK-V7-LE-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_24_8_16:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: ldrb r0, [r0]
|
|
; CHECK-BE-NEXT: lsls r0, r0, #16
|
|
; CHECK-BE-NEXT: movne r0, #1
|
|
; CHECK-BE-NEXT: mov pc, lr
|
|
;
|
|
; CHECK-V7-BE-LABEL: test_24_8_16:
|
|
; CHECK-V7-BE: @ %bb.0:
|
|
; CHECK-V7-BE-NEXT: ldrb r0, [r0]
|
|
; CHECK-V7-BE-NEXT: lsls r0, r0, #16
|
|
; CHECK-V7-BE-NEXT: movwne r0, #1
|
|
; CHECK-V7-BE-NEXT: bx lr
|
|
%a = load i24, ptr %y
|
|
%b = and i24 %a, u0xff0000
|
|
%cmp = icmp ne i24 %b, 0
|
|
ret i1 %cmp
|
|
}
|