Before llvm20, (void)__sync_fetch_and_add(...) always generates locked xadd insns. In linux kernel upstream discussion [1], it is found that for arm64 architecture, the original semantics of (void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is preferred in order for jit to emit proper native barrier insns. In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will generate the following insns: - for cpu v1/v2: locked xadd insns to keep backward compatibility - for cpu v3/v4: __atomic_fetch_add() insns To ensure proper barrier semantics for (void)__sync_fetch_and_add(...), cpu v3/v4 is recommended. This patch enables cpu=v3 as the default cpu version. For users wanting to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc command line. [1] https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f [2] https://github.com/llvm/llvm-project/pull/101428 [3] https://github.com/llvm/llvm-project/pull/106494
46 lines
1.2 KiB
LLVM
46 lines
1.2 KiB
LLVM
; RUN: llc -march=bpfel -mcpu=v1 -show-mc-encoding < %s | FileCheck %s
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define i8 @mov(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: mov:
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; CHECK: r0 = r2 # encoding: [0xbf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
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; CHECK: exit # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
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ret i8 %b
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}
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define i8 @add(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: add:
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; CHECK: r0 = r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
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; CHECK: r0 += r2 # encoding: [0x0f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
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%1 = add i8 %a, %b
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ret i8 %1
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}
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define i8 @and(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: and:
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; CHECK: r0 &= r2 # encoding: [0x5f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
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%1 = and i8 %a, %b
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ret i8 %1
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}
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define i8 @bis(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: bis:
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; CHECK: r0 |= r2 # encoding: [0x4f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
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%1 = or i8 %a, %b
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ret i8 %1
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}
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define i8 @xorand(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: xorand:
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; CHECK: r2 ^= -1 # encoding: [0xa7,0x02,0x00,0x00,0xff,0xff,0xff,0xff]
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%1 = xor i8 %b, -1
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%2 = and i8 %a, %1
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ret i8 %2
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}
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define i8 @xor(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: xor:
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; CHECK: r0 ^= r2 # encoding: [0xaf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
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%1 = xor i8 %a, %b
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ret i8 %1
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}
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