7852ebc088
Before llvm20, (void)__sync_fetch_and_add(...) always generates locked xadd insns. In linux kernel upstream discussion [1], it is found that for arm64 architecture, the original semantics of (void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is preferred in order for jit to emit proper native barrier insns. In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will generate the following insns: - for cpu v1/v2: locked xadd insns to keep backward compatibility - for cpu v3/v4: __atomic_fetch_add() insns To ensure proper barrier semantics for (void)__sync_fetch_and_add(...), cpu v3/v4 is recommended. This patch enables cpu=v3 as the default cpu version. For users wanting to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc command line. [1] https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f [2] https://github.com/llvm/llvm-project/pull/101428 [3] https://github.com/llvm/llvm-project/pull/106494
86 lines
2.4 KiB
LLVM
86 lines
2.4 KiB
LLVM
; RUN: llc < %s -march=bpf -mcpu=v1 -verify-machineinstrs | FileCheck %s
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; Source code:
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; struct xdp_md {
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; unsigned data;
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; unsigned data_end;
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; };
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;
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; int gbl;
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; int xdp_dummy(struct xdp_md *xdp)
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; {
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; char tmp;
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; long addr;
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;
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; if (gbl) {
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; long addr1 = (long)xdp->data;
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; tmp = *(char *)addr1;
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; if (tmp == 1)
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; return 3;
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; } else {
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; tmp = *(volatile char *)(long)xdp->data_end;
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; if (tmp == 1)
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; return 2;
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; }
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; addr = (long)xdp->data;
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; tmp = *(volatile char *)addr;
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; if (tmp == 0)
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; return 1;
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; return 0;
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; }
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%struct.xdp_md = type { i32, i32 }
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@gbl = common local_unnamed_addr global i32 0, align 4
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; Function Attrs: norecurse nounwind
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define i32 @xdp_dummy(ptr nocapture readonly %xdp) local_unnamed_addr #0 {
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entry:
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%0 = load i32, ptr @gbl, align 4
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%tobool = icmp eq i32 %0, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%1 = load i32, ptr %xdp, align 4
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%conv = zext i32 %1 to i64
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%2 = inttoptr i64 %conv to ptr
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%3 = load i8, ptr %2, align 1
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%cmp = icmp eq i8 %3, 1
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br i1 %cmp, label %cleanup20, label %if.end12
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; CHECK: r1 = *(u32 *)(r1 + 0)
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; CHECK: r2 = *(u8 *)(r1 + 0)
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if.else: ; preds = %entry
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%data_end = getelementptr inbounds %struct.xdp_md, ptr %xdp, i64 0, i32 1
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%4 = load i32, ptr %data_end, align 4
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%conv6 = zext i32 %4 to i64
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; CHECK: r2 = *(u32 *)(r1 + 4)
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%5 = inttoptr i64 %conv6 to ptr
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%6 = load volatile i8, ptr %5, align 1
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%cmp8 = icmp eq i8 %6, 1
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br i1 %cmp8, label %cleanup20, label %if.else.if.end12_crit_edge
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if.else.if.end12_crit_edge: ; preds = %if.else
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%.pre = load i32, ptr %xdp, align 4
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br label %if.end12
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; CHECK: r1 = *(u32 *)(r1 + 0)
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if.end12: ; preds = %if.else.if.end12_crit_edge, %if.then
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%7 = phi i32 [ %.pre, %if.else.if.end12_crit_edge ], [ %1, %if.then ]
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%conv14 = zext i32 %7 to i64
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; CHECK-NOT: r1 <<= 32
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; CHECK-NOT: r1 >>= 32
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%8 = inttoptr i64 %conv14 to ptr
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%9 = load volatile i8, ptr %8, align 1
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; CHECK: r1 = *(u8 *)(r1 + 0)
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%cmp16 = icmp eq i8 %9, 0
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%.28 = zext i1 %cmp16 to i32
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br label %cleanup20
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cleanup20: ; preds = %if.then, %if.end12, %if.else
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%retval.1 = phi i32 [ 3, %if.then ], [ 2, %if.else ], [ %.28, %if.end12 ]
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ret i32 %retval.1
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}
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attributes #0 = { norecurse nounwind }
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