f7a96dc664
Prior to this patch, both `pcaddu18i` and `jirl` were marked as scheduling boundaries to prevent instruction reordering that would disrupt their adjacency. However, in certain cases, epilogues were still being inserted between these two instructions, breaking the required proximity. This patch ensures that `pcaddu18i` and `jirl` remain adjacent even in the presence of epilogues, maintaining correct relocation behavior for tail calls on LoongArch.
121 lines
3.9 KiB
LLVM
121 lines
3.9 KiB
LLVM
; RUN: llc --mtriple=loongarch64 --relocation-model=pic \
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; RUN: --code-model=medium < %s | FileCheck --check-prefix=MEDIUM %s
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; RUN: llc --mtriple=loongarch64 --relocation-model=pic \
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; RUN: --code-model=large < %s | FileCheck --check-prefix=LARGE %s
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; RUN: llc --mtriple=loongarch64 --relocation-model=pic \
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; RUN: --enable-tlsdesc --code-model=large < %s | \
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; RUN: FileCheck --check-prefix=LARGEDESC %s
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; Check the adjancency of pseudo-instruction expansions to ensure
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; compliance with psABI requirements:
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; https://github.com/loongson/la-abi-specs/releases/tag/v2.30
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declare void @llvm.memset.p0.i64(ptr, i8, i64, i1)
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define void @call_external_sym(ptr %dst) {
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; LARGE-LABEL: call_external_sym:
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; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %pc_hi20(memset)
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; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %pc_lo12(memset)
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; LARGE-NEXT: lu32i.d [[REG2]], %pc64_lo20(memset)
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; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %pc64_hi12(memset)
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entry:
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call void @llvm.memset.p0.i64(ptr %dst, i8 0, i64 1000, i1 false)
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ret void
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}
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declare i32 @callee_tail(i32 %i)
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define i32 @caller_call_tail(i32 %i) nounwind {
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; MEDIUM-LABEL: caller_call_tail:
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; MEDIUM: pcaddu18i $t8, %call36(callee_tail)
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; MEDIUM-NEXT: jr $t8
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;
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; LARGE-LABEL: caller_call_tail:
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; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %got_pc_hi20(callee_tail)
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; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %got_pc_lo12(callee_tail)
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; LARGE-NEXT: lu32i.d [[REG2]], %got64_pc_lo20(callee_tail)
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; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %got64_pc_hi12(callee_tail)
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entry:
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call i32 @callee_tail(i32 %i)
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%r = tail call i32 @callee_tail(i32 %i)
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ret i32 %r
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}
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@ie = external thread_local(initialexec) global i32
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define void @test_la_tls_ie(i32 signext %n) {
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; LARGE-LABEL: test_la_tls_ie:
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; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %ie_pc_hi20(ie)
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; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %ie_pc_lo12(ie)
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; LARGE-NEXT: lu32i.d [[REG2]], %ie64_pc_lo20(ie)
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; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %ie64_pc_hi12(ie)
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entry:
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br label %loop
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loop:
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%i = phi i32 [ %inc, %loop ], [ 0, %entry ]
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%0 = load volatile i32, ptr @ie, align 4
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%inc = add nuw nsw i32 %i, 1
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%cmp = icmp slt i32 %inc, %n
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br i1 %cmp, label %loop, label %ret
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ret:
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ret void
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}
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@ld = external thread_local(localdynamic) global i32
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define void @test_la_tls_ld(i32 signext %n) {
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; LARGE-LABEL: test_la_tls_ld:
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; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %ld_pc_hi20(ld)
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; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %got_pc_lo12(ld)
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; LARGE-NEXT: lu32i.d [[REG2]], %got64_pc_lo20(ld)
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; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %got64_pc_hi12(ld)
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entry:
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br label %loop
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loop:
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%i = phi i32 [ %inc, %loop ], [ 0, %entry ]
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%0 = load volatile i32, ptr @ld, align 4
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%inc = add nuw nsw i32 %i, 1
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%cmp = icmp slt i32 %inc, %n
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br i1 %cmp, label %loop, label %ret
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ret:
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ret void
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}
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@gd = external thread_local global i32
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define void @test_la_tls_gd(i32 signext %n) nounwind {
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; LARGE-LABEL: test_la_tls_gd:
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; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %gd_pc_hi20(gd)
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; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %got_pc_lo12(gd)
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; LARGE-NEXT: lu32i.d [[REG2]], %got64_pc_lo20(gd)
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; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %got64_pc_hi12(gd)
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entry:
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br label %loop
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loop:
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%i = phi i32 [ %inc, %loop ], [ 0, %entry ]
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%0 = load volatile i32, ptr @gd, align 4
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%inc = add nuw nsw i32 %i, 1
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%cmp = icmp slt i32 %inc, %n
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br i1 %cmp, label %loop, label %ret
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ret:
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ret void
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}
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@unspecified = external thread_local global i32
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define ptr @test_la_tls_desc() nounwind {
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; LARGEDESC-LABEL: test_la_tls_desc:
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; LARGEDESC: pcalau12i [[REG1:\$[a-z0-9]+]], %desc_pc_hi20(unspecified)
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; LARGEDESC-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %desc_pc_lo12(unspecified)
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; LARGEDESC-NEXT: lu32i.d [[REG2]], %desc64_pc_lo20(unspecified)
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; LARGEDESC-NEXT: lu52i.d [[REG2]], [[REG2]], %desc64_pc_hi12(unspecified)
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entry:
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ret ptr @unspecified
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}
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