ebbc5de7db
The m68k backend will always emit external calls (including libcalls) with PC-relative PLT relocations, even when in non-pic mode or -fno-plt is used. This is unexpected, as other function calls are emitted with absolute addressing, and a static code modes suggests that there is no PLT. It also leads to a miscompilation where the call instruction emitted expects an immediate address, while the relocation emitted for that instruction is PC-relative. This miscompilation can even be seen in the default C function in godbolt: https://godbolt.org/z/zEoazovzo Fix the issue by classifying external function references based upon the pic mode. This triggers a change in the static code model, making it more in line with the expected behaviour and allowing use of this backend in more bare-metal situations where a PLT does not exist. The change avoids the issue where we emit a PLT32 relocation for an absolute call, and makes libcalls and other external calls use absolute addressing modes when a static code model is desired. Further work should be done in instruction lowering and validation to ensure that miscompilations of the same type don't occur.
266 lines
7.0 KiB
LLVM
266 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k-linux | FileCheck %s
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define i32 @mul4_32(i32 %A) {
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; CHECK-LABEL: mul4_32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: lsl.l #2, %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, 4
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ret i32 %mul
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}
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define i64 @mul4_64(i64 %A) {
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; CHECK-LABEL: mul4_64:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -8
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; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
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; CHECK-NEXT: moveq #30, %d0
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; CHECK-NEXT: move.l (12,%sp), %d1
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; CHECK-NEXT: move.l %d1, %d2
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; CHECK-NEXT: lsr.l %d0, %d2
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; CHECK-NEXT: move.l (8,%sp), %d0
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; CHECK-NEXT: lsl.l #2, %d0
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; CHECK-NEXT: or.l %d2, %d0
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; CHECK-NEXT: lsl.l #2, %d1
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; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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%mul = mul i64 %A, 4
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ret i64 %mul
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}
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define i32 @mul4096_32(i32 %A) {
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; CHECK-LABEL: mul4096_32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: moveq #12, %d1
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: lsl.l %d1, %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, 4096
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ret i32 %mul
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}
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define i64 @mul4096_64(i64 %A) {
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; CHECK-LABEL: mul4096_64:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #8, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -12
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; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
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; CHECK-NEXT: moveq #20, %d0
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; CHECK-NEXT: move.l (16,%sp), %d1
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; CHECK-NEXT: move.l %d1, %d2
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; CHECK-NEXT: lsr.l %d0, %d2
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; CHECK-NEXT: moveq #12, %d3
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; CHECK-NEXT: move.l (12,%sp), %d0
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; CHECK-NEXT: lsl.l %d3, %d0
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; CHECK-NEXT: or.l %d2, %d0
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; CHECK-NEXT: lsl.l %d3, %d1
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; CHECK-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
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; CHECK-NEXT: adda.l #8, %sp
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; CHECK-NEXT: rts
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%mul = mul i64 %A, 4096
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ret i64 %mul
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}
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define i32 @mulmin4096_32(i32 %A) {
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; CHECK-LABEL: mulmin4096_32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: moveq #12, %d1
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: lsl.l %d1, %d0
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; CHECK-NEXT: neg.l %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, -4096
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ret i32 %mul
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}
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define i64 @mulmin4096_64(i64 %A) {
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; CHECK-LABEL: mulmin4096_64:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #8, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -12
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; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
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; CHECK-NEXT: moveq #20, %d0
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; CHECK-NEXT: move.l (16,%sp), %d1
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; CHECK-NEXT: move.l %d1, %d2
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; CHECK-NEXT: lsr.l %d0, %d2
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; CHECK-NEXT: moveq #12, %d3
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; CHECK-NEXT: move.l (12,%sp), %d0
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; CHECK-NEXT: lsl.l %d3, %d0
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; CHECK-NEXT: or.l %d2, %d0
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; CHECK-NEXT: lsl.l %d3, %d1
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; CHECK-NEXT: neg.l %d1
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; CHECK-NEXT: negx.l %d0
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; CHECK-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
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; CHECK-NEXT: adda.l #8, %sp
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; CHECK-NEXT: rts
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%mul = mul i64 %A, -4096
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ret i64 %mul
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}
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; No i32 multiply for M68000
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define i32 @mul_32(i32 %a, i32 %b) {
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; CHECK-LABEL: mul_32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -16
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; CHECK-NEXT: move.l (20,%sp), (4,%sp)
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; CHECK-NEXT: move.l (16,%sp), (%sp)
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; CHECK-NEXT: jsr __mulsi3
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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%mul = mul i32 %a, %b
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ret i32 %mul
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}
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; Lower to shift and add if we can
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define i32 @mul3_32(i32 %A) {
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; CHECK-LABEL: mul3_32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: lsl.l #1, %d0
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; CHECK-NEXT: add.l %d1, %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, 3
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ret i32 %mul
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}
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define i32 @mul40_32(i32 %A) {
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; CHECK-LABEL: mul40_32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: move.l %d0, %d1
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; CHECK-NEXT: lsl.l #3, %d1
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; CHECK-NEXT: lsl.l #5, %d0
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; CHECK-NEXT: add.l %d1, %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, 40
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ret i32 %mul
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}
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; No i64 multiply for M68000
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define i64 @mul_64(i64 %a, i64 %b) {
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; CHECK-LABEL: mul_64:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #20, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -24
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; CHECK-NEXT: move.l (36,%sp), (12,%sp)
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; CHECK-NEXT: move.l (32,%sp), (8,%sp)
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; CHECK-NEXT: move.l (28,%sp), (4,%sp)
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; CHECK-NEXT: move.l (24,%sp), (%sp)
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; CHECK-NEXT: jsr __muldi3
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; CHECK-NEXT: adda.l #20, %sp
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; CHECK-NEXT: rts
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%mul = mul i64 %a, %b
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ret i64 %mul
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}
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define i64 @mul3_64(i64 %A) {
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; CHECK-LABEL: mul3_64:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #20, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -24
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; CHECK-NEXT: move.l #3, (12,%sp)
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; CHECK-NEXT: move.l #0, (8,%sp)
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; CHECK-NEXT: move.l (28,%sp), (4,%sp)
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; CHECK-NEXT: move.l (24,%sp), (%sp)
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; CHECK-NEXT: jsr __muldi3
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; CHECK-NEXT: adda.l #20, %sp
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; CHECK-NEXT: rts
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%mul = mul i64 %A, 3
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ret i64 %mul
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}
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define i64 @mul40_64(i64 %A) {
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; CHECK-LABEL: mul40_64:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #20, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -24
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; CHECK-NEXT: move.l #40, (12,%sp)
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; CHECK-NEXT: move.l #0, (8,%sp)
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; CHECK-NEXT: move.l (28,%sp), (4,%sp)
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; CHECK-NEXT: move.l (24,%sp), (%sp)
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; CHECK-NEXT: jsr __muldi3
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; CHECK-NEXT: adda.l #20, %sp
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; CHECK-NEXT: rts
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%mul = mul i64 %A, 40
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ret i64 %mul
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}
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define i32 @mul4_32_minsize(i32 %A) minsize {
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; CHECK-LABEL: mul4_32_minsize:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: lsl.l #2, %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, 4
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ret i32 %mul
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}
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define i32 @mul40_32_minsize(i32 %A) minsize {
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; CHECK-LABEL: mul40_32_minsize:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: move.l %d0, %d1
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; CHECK-NEXT: lsl.l #3, %d1
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; CHECK-NEXT: lsl.l #5, %d0
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; CHECK-NEXT: add.l %d1, %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, 40
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ret i32 %mul
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}
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define i32 @mul33_32(i32 %A) {
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; CHECK-LABEL: mul33_32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: lsl.l #5, %d0
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; CHECK-NEXT: add.l %d1, %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, 33
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ret i32 %mul
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}
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define i32 @mul31_32(i32 %A) {
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; CHECK-LABEL: mul31_32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: lsl.l #5, %d0
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; CHECK-NEXT: sub.l %d1, %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, 31
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ret i32 %mul
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}
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define i32 @mul0_32(i32 %A) {
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; CHECK-LABEL: mul0_32:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: moveq #0, %d0
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; CHECK-NEXT: rts
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%mul = mul i32 %A, 0
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ret i32 %mul
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}
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