Akshat Oke 6360652e9f Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) (#112492) ...

A reland but not an exact copy as `VRegInfo.Flags` from the parser is
now an int8 instead of a vector; so only need to copy over the value.

2024-10-21 13:44:09 +05:30

..

custom-pseudo-source-values.ll

[AMDGPU] Use resource base for buffer instruction MachineMemOperands

2023-06-05 17:06:57 +00:00

dead-flag-on-use-operand-parse-error.mir

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empty-custom-regmask.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

expected-target-index-name.mir

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intrinsics.mir

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invalid-frame-index2.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-invalid-fixed-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-invalid-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-no-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-target-index-operand.mir

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killed-flag-on-def-parse-error.mir

MIRParser: Fix asserting with invalid flags on machine operands

2022-04-05 21:46:26 -04:00

lit.local.cfg

[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm

2023-05-17 17:03:15 +02:00

llc-target-cpu-attr-from-cmdline-ir.mir

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llc-target-cpu-attr-from-cmdline.mir

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long-branch-reg-all-sgpr-used.ll

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

machine-function-info-after-pei.ll

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

machine-function-info-dynlds-align-invalid-case.mir

[amdgpu] Add codegen support for HIP dynamic shared memory.

2020-08-20 21:29:18 -04:00

machine-function-info-long-branch-reg-debug.ll

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

machine-function-info-long-branch-reg.ll

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

machine-function-info-no-ir.mir

Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) (#112492)

2024-10-21 13:44:09 +05:30

machine-function-info-register-parse-error1.mir

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machine-function-info-register-parse-error2.mir

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machine-function-info.ll

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

machine-metadata-error.mir

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

machine-metadata.mir

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

mfi-frame-offset-reg-class.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

mfi-parse-error-frame-offset-reg.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

mfi-parse-error-scratch-rsrc-reg.mir

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mfi-parse-error-stack-ptr-offset-reg.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

mfi-scratch-rsrc-reg-reg-class.mir

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mfi-stack-ptr-offset-reg-class.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

mir-canon-multi.mir

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mircanon-memoperands.mir

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noconvergent-invalid.mir

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noconvergent.mir

[GlobalISel] introduce MIFlag::NoConvergent

2023-08-20 21:14:46 +05:30

parse-order-reserved-regs.mir

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sgpr-for-exec-copy-invalid-reg.mir

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stack-id-assert.mir

[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001)

2024-03-18 10:37:59 -04:00

stack-id.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

subreg-def-is-not-ssa.mir

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syncscopes.mir

[CodeGen] Convert tests to opaque pointers (NFC)

2024-02-05 14:07:09 +01:00

target-flags.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-16 21:54:58 -08:00

target-index-operands.mir

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target-memoperands.mir

[AMDGPU] Add mark last scratch load pass (#75512)

2024-01-18 09:36:44 +01:00

vgpr-for-agpr-copy-invalid-reg.mir

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virtreg-uses-unallocatable-class.mir

[Support] Implement LLVM_ENABLE_REVERSE_ITERATION for StringMap

2023-07-21 08:46:51 -07:00

wwm-reserved-regs-invalid-reg.mir

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wwm-reserved-regs-not-a-reg.mir

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wwm-reserved-regs.mir

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