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clang-p2996/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir
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Sergei Barannikov 3fee8b3469 [GISel] LegalizationArtifactCombiner: Elide redundant G_SEXT_INREG (#93687) 
This is similar to 373c343a, but for targets with zero-or-negative-one
booleans.
The difference in tests is mostly due to G_SEXT_INREG being illegal for
some targets, in which case it gets expanded into G_SHL/G_ASHR pair,
which is not currently optimized by the combiner.
2024-05-30 12:40:42 +03:00
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add_vec_builtin.ll
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add_vec.ll
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add.ll
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aggregate_struct_return.ll
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bitreverse.ll
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bitwise.ll
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branch.ll
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brindirect.ll
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bswap.ll
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call.ll
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ceil_and_floor.ll
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constants.ll
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ctlz.ll
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ctpop.ll
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cttz.ll
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dyn_stackalloc.ll
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fabs_vec_builtin.ll
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fabs_vec.ll
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fabs.ll
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fcmp.ll
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fence.ll
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float_args.ll
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float_arithmetic_operations.ll
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float_constants.ll
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floating_point_vec_arithmetic_operations_builtin.ll
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floating_point_vec_arithmetic_operations.ll
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fpext_and_fptrunc.ll
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fptosi_and_fptoui.ll
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fsqrt_vec_builtin.ll
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fsqrt_vec.ll
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fsqrt.ll
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global_address_pic.ll
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global_address.ll
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icmp.ll
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implicit_def.ll
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inttoptr_and_ptrtoint.ll
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jump_table_and_brjt.ll
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load_4_unaligned.ll
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load_atomic.ll
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load_split_because_of_memsize_or_align.ll
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load_store_fold.ll
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load_store_vec.ll
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load.ll
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long_ambiguous_chain_s32.ll
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long_ambiguous_chain_s64.ll
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mul_vec_builtin.ll
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mul_vec.ll
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mul.ll
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phi.ll
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pointers.ll
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rem_and_div_vec_builtin.ll
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rem_and_div_vec.ll
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rem_and_div.ll
[GISel] LegalizationArtifactCombiner: Elide redundant G_SEXT_INREG (#93687)
2024-05-30 12:40:42 +03:00
ret.ll
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select.ll
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sitofp_and_uitofp.ll
[GISel] LegalizationArtifactCombiner: Elide redundant G_SEXT_INREG (#93687)
2024-05-30 12:40:42 +03:00
sret_pointer.ll
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stack_args.ll
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store_4_unaligned.ll
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store_split_because_of_memsize_or_align.ll
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store.ll
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sub_vec_builtin.ll
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sub_vec.ll
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sub.ll
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test_TypeInfoforMF.ll
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trap.ll
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trunc.ll
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truncStore_and_aExtLoad.ll
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var_arg.ll
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zext_and_sext.ll
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zextLoad_and_sextLoad.ll
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