401d123a1f
Before this patch, redundant COPY couldn't be removed for the following case: ``` $R0 = OP ... ... // Read of %R0 $R1 = COPY killed $R0 ``` This patch adds support for tracking the users of the source register during backward propagation, so that we can remove the redundant COPY in the above case and optimize it to: ``` $R1 = OP ... ... // Replace all uses of %R0 with $R1 ```
608 lines
19 KiB
LLVM
608 lines
19 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS2
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; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP32R6
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS3
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS3
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP64R6
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips \
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; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
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; RUN: FileCheck %s -check-prefix=MMR3
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \
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; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
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; RUN: FileCheck %s -check-prefix=MMR6
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define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
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; MIPS2-LABEL: sdiv_i1:
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; MIPS2: # %bb.0: # %entry
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; MIPS2-NEXT: jr $ra
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; MIPS2-NEXT: move $2, $4
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;
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; GP32-LABEL: sdiv_i1:
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; GP32: # %bb.0: # %entry
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; GP32-NEXT: jr $ra
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; GP32-NEXT: move $2, $4
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;
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; GP32R6-LABEL: sdiv_i1:
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; GP32R6: # %bb.0: # %entry
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; GP32R6-NEXT: jr $ra
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; GP32R6-NEXT: move $2, $4
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;
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; MIPS3-LABEL: sdiv_i1:
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; MIPS3: # %bb.0: # %entry
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; MIPS3-NEXT: jr $ra
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; MIPS3-NEXT: move $2, $4
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;
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; GP64-LABEL: sdiv_i1:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: jr $ra
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; GP64-NEXT: move $2, $4
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;
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; GP64R6-LABEL: sdiv_i1:
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; GP64R6: # %bb.0: # %entry
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; GP64R6-NEXT: jr $ra
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; GP64R6-NEXT: move $2, $4
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;
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; MMR3-LABEL: sdiv_i1:
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; MMR3: # %bb.0: # %entry
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; MMR3-NEXT: move $2, $4
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; MMR3-NEXT: jrc $ra
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;
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; MMR6-LABEL: sdiv_i1:
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; MMR6: # %bb.0: # %entry
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; MMR6-NEXT: move $2, $4
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; MMR6-NEXT: jrc $ra
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entry:
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%r = sdiv i1 %a, %b
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ret i1 %r
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}
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define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) {
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; MIPS2-LABEL: sdiv_i8:
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; MIPS2: # %bb.0: # %entry
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; MIPS2-NEXT: div $zero, $4, $5
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; MIPS2-NEXT: teq $5, $zero, 7
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; MIPS2-NEXT: mflo $1
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; MIPS2-NEXT: sll $1, $1, 24
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; MIPS2-NEXT: jr $ra
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; MIPS2-NEXT: sra $2, $1, 24
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;
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; GP32R0R2-LABEL: sdiv_i8:
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; GP32R0R2: # %bb.0: # %entry
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; GP32R0R2-NEXT: div $zero, $4, $5
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; GP32R0R2-NEXT: teq $5, $zero, 7
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; GP32R0R2-NEXT: mflo $1
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; GP32R0R2-NEXT: sll $1, $1, 24
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; GP32R0R2-NEXT: jr $ra
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; GP32R0R2-NEXT: sra $2, $1, 24
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;
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; GP32R2R5-LABEL: sdiv_i8:
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; GP32R2R5: # %bb.0: # %entry
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; GP32R2R5-NEXT: div $zero, $4, $5
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; GP32R2R5-NEXT: teq $5, $zero, 7
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; GP32R2R5-NEXT: mflo $1
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; GP32R2R5-NEXT: jr $ra
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; GP32R2R5-NEXT: seb $2, $1
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;
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; GP32R6-LABEL: sdiv_i8:
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; GP32R6: # %bb.0: # %entry
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; GP32R6-NEXT: div $1, $4, $5
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; GP32R6-NEXT: teq $5, $zero, 7
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; GP32R6-NEXT: jr $ra
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; GP32R6-NEXT: seb $2, $1
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;
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; MIPS3-LABEL: sdiv_i8:
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; MIPS3: # %bb.0: # %entry
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; MIPS3-NEXT: div $zero, $4, $5
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; MIPS3-NEXT: teq $5, $zero, 7
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; MIPS3-NEXT: mflo $1
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; MIPS3-NEXT: sll $1, $1, 24
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; MIPS3-NEXT: jr $ra
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; MIPS3-NEXT: sra $2, $1, 24
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;
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; GP64R0R1-LABEL: sdiv_i8:
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; GP64R0R1: # %bb.0: # %entry
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; GP64R0R1-NEXT: div $zero, $4, $5
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; GP64R0R1-NEXT: teq $5, $zero, 7
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; GP64R0R1-NEXT: mflo $1
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; GP64R0R1-NEXT: sll $1, $1, 24
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; GP64R0R1-NEXT: jr $ra
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; GP64R0R1-NEXT: sra $2, $1, 24
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;
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; GP64R2R5-LABEL: sdiv_i8:
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; GP64R2R5: # %bb.0: # %entry
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; GP64R2R5-NEXT: div $zero, $4, $5
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; GP64R2R5-NEXT: teq $5, $zero, 7
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; GP64R2R5-NEXT: mflo $1
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; GP64R2R5-NEXT: jr $ra
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; GP64R2R5-NEXT: seb $2, $1
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;
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; GP64R6-LABEL: sdiv_i8:
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; GP64R6: # %bb.0: # %entry
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; GP64R6-NEXT: div $1, $4, $5
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; GP64R6-NEXT: teq $5, $zero, 7
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; GP64R6-NEXT: jr $ra
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; GP64R6-NEXT: seb $2, $1
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;
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; MMR3-LABEL: sdiv_i8:
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; MMR3: # %bb.0: # %entry
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; MMR3-NEXT: div $zero, $4, $5
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; MMR3-NEXT: teq $5, $zero, 7
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; MMR3-NEXT: mflo16 $1
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; MMR3-NEXT: jr $ra
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; MMR3-NEXT: seb $2, $1
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;
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; MMR6-LABEL: sdiv_i8:
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; MMR6: # %bb.0: # %entry
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; MMR6-NEXT: div $1, $4, $5
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; MMR6-NEXT: teq $5, $zero, 7
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; MMR6-NEXT: seb $2, $1
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; MMR6-NEXT: jrc $ra
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entry:
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%r = sdiv i8 %a, %b
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ret i8 %r
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}
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define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) {
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; MIPS2-LABEL: sdiv_i16:
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; MIPS2: # %bb.0: # %entry
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; MIPS2-NEXT: div $zero, $4, $5
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; MIPS2-NEXT: teq $5, $zero, 7
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; MIPS2-NEXT: mflo $1
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; MIPS2-NEXT: sll $1, $1, 16
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; MIPS2-NEXT: jr $ra
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; MIPS2-NEXT: sra $2, $1, 16
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;
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; GP32R0R2-LABEL: sdiv_i16:
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; GP32R0R2: # %bb.0: # %entry
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; GP32R0R2-NEXT: div $zero, $4, $5
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; GP32R0R2-NEXT: teq $5, $zero, 7
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; GP32R0R2-NEXT: mflo $1
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; GP32R0R2-NEXT: sll $1, $1, 16
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; GP32R0R2-NEXT: jr $ra
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; GP32R0R2-NEXT: sra $2, $1, 16
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;
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; GP32R2R5-LABEL: sdiv_i16:
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; GP32R2R5: # %bb.0: # %entry
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; GP32R2R5-NEXT: div $zero, $4, $5
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; GP32R2R5-NEXT: teq $5, $zero, 7
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; GP32R2R5-NEXT: mflo $1
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; GP32R2R5-NEXT: jr $ra
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; GP32R2R5-NEXT: seh $2, $1
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;
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; GP32R6-LABEL: sdiv_i16:
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; GP32R6: # %bb.0: # %entry
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; GP32R6-NEXT: div $1, $4, $5
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; GP32R6-NEXT: teq $5, $zero, 7
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; GP32R6-NEXT: jr $ra
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; GP32R6-NEXT: seh $2, $1
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;
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; MIPS3-LABEL: sdiv_i16:
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; MIPS3: # %bb.0: # %entry
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; MIPS3-NEXT: div $zero, $4, $5
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; MIPS3-NEXT: teq $5, $zero, 7
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; MIPS3-NEXT: mflo $1
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; MIPS3-NEXT: sll $1, $1, 16
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; MIPS3-NEXT: jr $ra
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; MIPS3-NEXT: sra $2, $1, 16
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;
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; GP64R0R1-LABEL: sdiv_i16:
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; GP64R0R1: # %bb.0: # %entry
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; GP64R0R1-NEXT: div $zero, $4, $5
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; GP64R0R1-NEXT: teq $5, $zero, 7
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; GP64R0R1-NEXT: mflo $1
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; GP64R0R1-NEXT: sll $1, $1, 16
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; GP64R0R1-NEXT: jr $ra
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; GP64R0R1-NEXT: sra $2, $1, 16
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;
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; GP64R2R5-LABEL: sdiv_i16:
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; GP64R2R5: # %bb.0: # %entry
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; GP64R2R5-NEXT: div $zero, $4, $5
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; GP64R2R5-NEXT: teq $5, $zero, 7
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; GP64R2R5-NEXT: mflo $1
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; GP64R2R5-NEXT: jr $ra
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; GP64R2R5-NEXT: seh $2, $1
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;
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; GP64R6-LABEL: sdiv_i16:
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; GP64R6: # %bb.0: # %entry
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; GP64R6-NEXT: div $1, $4, $5
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; GP64R6-NEXT: teq $5, $zero, 7
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; GP64R6-NEXT: jr $ra
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; GP64R6-NEXT: seh $2, $1
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;
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; MMR3-LABEL: sdiv_i16:
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; MMR3: # %bb.0: # %entry
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; MMR3-NEXT: div $zero, $4, $5
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; MMR3-NEXT: teq $5, $zero, 7
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; MMR3-NEXT: mflo16 $1
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; MMR3-NEXT: jr $ra
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; MMR3-NEXT: seh $2, $1
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;
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; MMR6-LABEL: sdiv_i16:
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; MMR6: # %bb.0: # %entry
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; MMR6-NEXT: div $1, $4, $5
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; MMR6-NEXT: teq $5, $zero, 7
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; MMR6-NEXT: seh $2, $1
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; MMR6-NEXT: jrc $ra
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entry:
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%r = sdiv i16 %a, %b
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ret i16 %r
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}
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define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) {
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; MIPS2-LABEL: sdiv_i32:
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; MIPS2: # %bb.0: # %entry
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; MIPS2-NEXT: div $zero, $4, $5
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; MIPS2-NEXT: teq $5, $zero, 7
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; MIPS2-NEXT: mflo $2
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; MIPS2-NEXT: jr $ra
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; MIPS2-NEXT: nop
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;
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; GP32-LABEL: sdiv_i32:
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; GP32: # %bb.0: # %entry
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; GP32-NEXT: div $zero, $4, $5
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; GP32-NEXT: teq $5, $zero, 7
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; GP32-NEXT: jr $ra
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; GP32-NEXT: mflo $2
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;
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; GP32R6-LABEL: sdiv_i32:
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; GP32R6: # %bb.0: # %entry
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; GP32R6-NEXT: div $2, $4, $5
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; GP32R6-NEXT: teq $5, $zero, 7
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; GP32R6-NEXT: jrc $ra
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;
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; MIPS3-LABEL: sdiv_i32:
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; MIPS3: # %bb.0: # %entry
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; MIPS3-NEXT: div $zero, $4, $5
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; MIPS3-NEXT: teq $5, $zero, 7
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; MIPS3-NEXT: mflo $2
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; MIPS3-NEXT: jr $ra
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; MIPS3-NEXT: nop
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;
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; GP64-LABEL: sdiv_i32:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: div $zero, $4, $5
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; GP64-NEXT: teq $5, $zero, 7
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; GP64-NEXT: jr $ra
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; GP64-NEXT: mflo $2
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;
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; GP64R6-LABEL: sdiv_i32:
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; GP64R6: # %bb.0: # %entry
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; GP64R6-NEXT: div $2, $4, $5
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; GP64R6-NEXT: teq $5, $zero, 7
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; GP64R6-NEXT: jrc $ra
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;
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; MMR3-LABEL: sdiv_i32:
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; MMR3: # %bb.0: # %entry
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; MMR3-NEXT: div $zero, $4, $5
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; MMR3-NEXT: teq $5, $zero, 7
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; MMR3-NEXT: mflo16 $2
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; MMR3-NEXT: jrc $ra
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;
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; MMR6-LABEL: sdiv_i32:
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; MMR6: # %bb.0: # %entry
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; MMR6-NEXT: div $2, $4, $5
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; MMR6-NEXT: teq $5, $zero, 7
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; MMR6-NEXT: jrc $ra
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entry:
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%r = sdiv i32 %a, %b
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ret i32 %r
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}
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define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
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; MIPS2-LABEL: sdiv_i64:
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; MIPS2: # %bb.0: # %entry
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; MIPS2-NEXT: lui $2, %hi(_gp_disp)
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; MIPS2-NEXT: addiu $2, $2, %lo(_gp_disp)
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; MIPS2-NEXT: addiu $sp, $sp, -24
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; MIPS2-NEXT: .cfi_def_cfa_offset 24
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; MIPS2-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; MIPS2-NEXT: .cfi_offset 31, -4
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; MIPS2-NEXT: addu $gp, $2, $25
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; MIPS2-NEXT: lw $25, %call16(__divdi3)($gp)
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; MIPS2-NEXT: jalr $25
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; MIPS2-NEXT: nop
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; MIPS2-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MIPS2-NEXT: jr $ra
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; MIPS2-NEXT: addiu $sp, $sp, 24
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;
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; GP32-LABEL: sdiv_i64:
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; GP32: # %bb.0: # %entry
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; GP32-NEXT: lui $2, %hi(_gp_disp)
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; GP32-NEXT: addiu $2, $2, %lo(_gp_disp)
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; GP32-NEXT: addiu $sp, $sp, -24
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; GP32-NEXT: .cfi_def_cfa_offset 24
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; GP32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; GP32-NEXT: .cfi_offset 31, -4
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; GP32-NEXT: addu $gp, $2, $25
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; GP32-NEXT: lw $25, %call16(__divdi3)($gp)
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; GP32-NEXT: jalr $25
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; GP32-NEXT: nop
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; GP32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; GP32-NEXT: jr $ra
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; GP32-NEXT: addiu $sp, $sp, 24
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;
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; GP32R6-LABEL: sdiv_i64:
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; GP32R6: # %bb.0: # %entry
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; GP32R6-NEXT: lui $2, %hi(_gp_disp)
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; GP32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
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; GP32R6-NEXT: addiu $sp, $sp, -24
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; GP32R6-NEXT: .cfi_def_cfa_offset 24
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; GP32R6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; GP32R6-NEXT: .cfi_offset 31, -4
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; GP32R6-NEXT: addu $gp, $2, $25
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; GP32R6-NEXT: lw $25, %call16(__divdi3)($gp)
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; GP32R6-NEXT: jalrc $25
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; GP32R6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
|
; GP32R6-NEXT: jr $ra
|
|
; GP32R6-NEXT: addiu $sp, $sp, 24
|
|
;
|
|
; MIPS3-LABEL: sdiv_i64:
|
|
; MIPS3: # %bb.0: # %entry
|
|
; MIPS3-NEXT: ddiv $zero, $4, $5
|
|
; MIPS3-NEXT: teq $5, $zero, 7
|
|
; MIPS3-NEXT: mflo $2
|
|
; MIPS3-NEXT: jr $ra
|
|
; MIPS3-NEXT: nop
|
|
;
|
|
; GP64-LABEL: sdiv_i64:
|
|
; GP64: # %bb.0: # %entry
|
|
; GP64-NEXT: ddiv $zero, $4, $5
|
|
; GP64-NEXT: teq $5, $zero, 7
|
|
; GP64-NEXT: jr $ra
|
|
; GP64-NEXT: mflo $2
|
|
;
|
|
; GP64R6-LABEL: sdiv_i64:
|
|
; GP64R6: # %bb.0: # %entry
|
|
; GP64R6-NEXT: ddiv $2, $4, $5
|
|
; GP64R6-NEXT: teq $5, $zero, 7
|
|
; GP64R6-NEXT: jrc $ra
|
|
;
|
|
; MMR3-LABEL: sdiv_i64:
|
|
; MMR3: # %bb.0: # %entry
|
|
; MMR3-NEXT: lui $2, %hi(_gp_disp)
|
|
; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
|
|
; MMR3-NEXT: addiusp -24
|
|
; MMR3-NEXT: .cfi_def_cfa_offset 24
|
|
; MMR3-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
|
; MMR3-NEXT: .cfi_offset 31, -4
|
|
; MMR3-NEXT: addu $gp, $2, $25
|
|
; MMR3-NEXT: lw $25, %call16(__divdi3)($gp)
|
|
; MMR3-NEXT: jalr $25
|
|
; MMR3-NEXT: nop
|
|
; MMR3-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
|
; MMR3-NEXT: addiusp 24
|
|
; MMR3-NEXT: jrc $ra
|
|
;
|
|
; MMR6-LABEL: sdiv_i64:
|
|
; MMR6: # %bb.0: # %entry
|
|
; MMR6-NEXT: lui $2, %hi(_gp_disp)
|
|
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
|
|
; MMR6-NEXT: addiu $sp, $sp, -24
|
|
; MMR6-NEXT: .cfi_def_cfa_offset 24
|
|
; MMR6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
|
; MMR6-NEXT: .cfi_offset 31, -4
|
|
; MMR6-NEXT: addu $gp, $2, $25
|
|
; MMR6-NEXT: lw $25, %call16(__divdi3)($gp)
|
|
; MMR6-NEXT: jalr $25
|
|
; MMR6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
|
; MMR6-NEXT: addiu $sp, $sp, 24
|
|
; MMR6-NEXT: jrc $ra
|
|
entry:
|
|
%r = sdiv i64 %a, %b
|
|
ret i64 %r
|
|
}
|
|
|
|
define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
|
|
; MIPS2-LABEL: sdiv_i128:
|
|
; MIPS2: # %bb.0: # %entry
|
|
; MIPS2-NEXT: lui $2, %hi(_gp_disp)
|
|
; MIPS2-NEXT: addiu $2, $2, %lo(_gp_disp)
|
|
; MIPS2-NEXT: addiu $sp, $sp, -40
|
|
; MIPS2-NEXT: .cfi_def_cfa_offset 40
|
|
; MIPS2-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
|
; MIPS2-NEXT: .cfi_offset 31, -4
|
|
; MIPS2-NEXT: addu $gp, $2, $25
|
|
; MIPS2-NEXT: lw $1, 60($sp)
|
|
; MIPS2-NEXT: lw $2, 64($sp)
|
|
; MIPS2-NEXT: lw $3, 68($sp)
|
|
; MIPS2-NEXT: sw $3, 28($sp)
|
|
; MIPS2-NEXT: sw $2, 24($sp)
|
|
; MIPS2-NEXT: sw $1, 20($sp)
|
|
; MIPS2-NEXT: lw $1, 56($sp)
|
|
; MIPS2-NEXT: sw $1, 16($sp)
|
|
; MIPS2-NEXT: lw $25, %call16(__divti3)($gp)
|
|
; MIPS2-NEXT: jalr $25
|
|
; MIPS2-NEXT: nop
|
|
; MIPS2-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
|
; MIPS2-NEXT: jr $ra
|
|
; MIPS2-NEXT: addiu $sp, $sp, 40
|
|
;
|
|
; GP32-LABEL: sdiv_i128:
|
|
; GP32: # %bb.0: # %entry
|
|
; GP32-NEXT: lui $2, %hi(_gp_disp)
|
|
; GP32-NEXT: addiu $2, $2, %lo(_gp_disp)
|
|
; GP32-NEXT: addiu $sp, $sp, -40
|
|
; GP32-NEXT: .cfi_def_cfa_offset 40
|
|
; GP32-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
|
; GP32-NEXT: .cfi_offset 31, -4
|
|
; GP32-NEXT: addu $gp, $2, $25
|
|
; GP32-NEXT: lw $1, 60($sp)
|
|
; GP32-NEXT: lw $2, 64($sp)
|
|
; GP32-NEXT: lw $3, 68($sp)
|
|
; GP32-NEXT: sw $3, 28($sp)
|
|
; GP32-NEXT: sw $2, 24($sp)
|
|
; GP32-NEXT: sw $1, 20($sp)
|
|
; GP32-NEXT: lw $1, 56($sp)
|
|
; GP32-NEXT: sw $1, 16($sp)
|
|
; GP32-NEXT: lw $25, %call16(__divti3)($gp)
|
|
; GP32-NEXT: jalr $25
|
|
; GP32-NEXT: nop
|
|
; GP32-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
|
; GP32-NEXT: jr $ra
|
|
; GP32-NEXT: addiu $sp, $sp, 40
|
|
;
|
|
; GP32R6-LABEL: sdiv_i128:
|
|
; GP32R6: # %bb.0: # %entry
|
|
; GP32R6-NEXT: lui $2, %hi(_gp_disp)
|
|
; GP32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
|
|
; GP32R6-NEXT: addiu $sp, $sp, -40
|
|
; GP32R6-NEXT: .cfi_def_cfa_offset 40
|
|
; GP32R6-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
|
; GP32R6-NEXT: .cfi_offset 31, -4
|
|
; GP32R6-NEXT: addu $gp, $2, $25
|
|
; GP32R6-NEXT: lw $1, 60($sp)
|
|
; GP32R6-NEXT: lw $2, 64($sp)
|
|
; GP32R6-NEXT: lw $3, 68($sp)
|
|
; GP32R6-NEXT: sw $3, 28($sp)
|
|
; GP32R6-NEXT: sw $2, 24($sp)
|
|
; GP32R6-NEXT: sw $1, 20($sp)
|
|
; GP32R6-NEXT: lw $1, 56($sp)
|
|
; GP32R6-NEXT: sw $1, 16($sp)
|
|
; GP32R6-NEXT: lw $25, %call16(__divti3)($gp)
|
|
; GP32R6-NEXT: jalrc $25
|
|
; GP32R6-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
|
; GP32R6-NEXT: jr $ra
|
|
; GP32R6-NEXT: addiu $sp, $sp, 40
|
|
;
|
|
; MIPS3-LABEL: sdiv_i128:
|
|
; MIPS3: # %bb.0: # %entry
|
|
; MIPS3-NEXT: daddiu $sp, $sp, -16
|
|
; MIPS3-NEXT: .cfi_def_cfa_offset 16
|
|
; MIPS3-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
|
|
; MIPS3-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
|
|
; MIPS3-NEXT: .cfi_offset 31, -8
|
|
; MIPS3-NEXT: .cfi_offset 28, -16
|
|
; MIPS3-NEXT: lui $1, %hi(%neg(%gp_rel(sdiv_i128)))
|
|
; MIPS3-NEXT: daddu $1, $1, $25
|
|
; MIPS3-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(sdiv_i128)))
|
|
; MIPS3-NEXT: ld $25, %call16(__divti3)($gp)
|
|
; MIPS3-NEXT: jalr $25
|
|
; MIPS3-NEXT: nop
|
|
; MIPS3-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
|
|
; MIPS3-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
|
|
; MIPS3-NEXT: jr $ra
|
|
; MIPS3-NEXT: daddiu $sp, $sp, 16
|
|
;
|
|
; GP64-LABEL: sdiv_i128:
|
|
; GP64: # %bb.0: # %entry
|
|
; GP64-NEXT: daddiu $sp, $sp, -16
|
|
; GP64-NEXT: .cfi_def_cfa_offset 16
|
|
; GP64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
|
|
; GP64-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
|
|
; GP64-NEXT: .cfi_offset 31, -8
|
|
; GP64-NEXT: .cfi_offset 28, -16
|
|
; GP64-NEXT: lui $1, %hi(%neg(%gp_rel(sdiv_i128)))
|
|
; GP64-NEXT: daddu $1, $1, $25
|
|
; GP64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(sdiv_i128)))
|
|
; GP64-NEXT: ld $25, %call16(__divti3)($gp)
|
|
; GP64-NEXT: jalr $25
|
|
; GP64-NEXT: nop
|
|
; GP64-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
|
|
; GP64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
|
|
; GP64-NEXT: jr $ra
|
|
; GP64-NEXT: daddiu $sp, $sp, 16
|
|
;
|
|
; GP64R6-LABEL: sdiv_i128:
|
|
; GP64R6: # %bb.0: # %entry
|
|
; GP64R6-NEXT: daddiu $sp, $sp, -16
|
|
; GP64R6-NEXT: .cfi_def_cfa_offset 16
|
|
; GP64R6-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
|
|
; GP64R6-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
|
|
; GP64R6-NEXT: .cfi_offset 31, -8
|
|
; GP64R6-NEXT: .cfi_offset 28, -16
|
|
; GP64R6-NEXT: lui $1, %hi(%neg(%gp_rel(sdiv_i128)))
|
|
; GP64R6-NEXT: daddu $1, $1, $25
|
|
; GP64R6-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(sdiv_i128)))
|
|
; GP64R6-NEXT: ld $25, %call16(__divti3)($gp)
|
|
; GP64R6-NEXT: jalrc $25
|
|
; GP64R6-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
|
|
; GP64R6-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
|
|
; GP64R6-NEXT: jr $ra
|
|
; GP64R6-NEXT: daddiu $sp, $sp, 16
|
|
;
|
|
; MMR3-LABEL: sdiv_i128:
|
|
; MMR3: # %bb.0: # %entry
|
|
; MMR3-NEXT: lui $2, %hi(_gp_disp)
|
|
; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
|
|
; MMR3-NEXT: addiusp -40
|
|
; MMR3-NEXT: .cfi_def_cfa_offset 40
|
|
; MMR3-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
|
; MMR3-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
|
|
; MMR3-NEXT: .cfi_offset 31, -4
|
|
; MMR3-NEXT: .cfi_offset 17, -8
|
|
; MMR3-NEXT: addu $gp, $2, $25
|
|
; MMR3-NEXT: move $1, $7
|
|
; MMR3-NEXT: lw $7, 60($sp)
|
|
; MMR3-NEXT: lw $17, 64($sp)
|
|
; MMR3-NEXT: lw $3, 68($sp)
|
|
; MMR3-NEXT: move $2, $sp
|
|
; MMR3-NEXT: sw16 $3, 28($2)
|
|
; MMR3-NEXT: sw16 $17, 24($2)
|
|
; MMR3-NEXT: sw16 $7, 20($2)
|
|
; MMR3-NEXT: lw $3, 56($sp)
|
|
; MMR3-NEXT: sw16 $3, 16($2)
|
|
; MMR3-NEXT: lw $25, %call16(__divti3)($gp)
|
|
; MMR3-NEXT: move $7, $1
|
|
; MMR3-NEXT: jalr $25
|
|
; MMR3-NEXT: nop
|
|
; MMR3-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
|
|
; MMR3-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
|
; MMR3-NEXT: addiusp 40
|
|
; MMR3-NEXT: jrc $ra
|
|
;
|
|
; MMR6-LABEL: sdiv_i128:
|
|
; MMR6: # %bb.0: # %entry
|
|
; MMR6-NEXT: lui $2, %hi(_gp_disp)
|
|
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
|
|
; MMR6-NEXT: addiu $sp, $sp, -40
|
|
; MMR6-NEXT: .cfi_def_cfa_offset 40
|
|
; MMR6-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
|
; MMR6-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
|
|
; MMR6-NEXT: .cfi_offset 31, -4
|
|
; MMR6-NEXT: .cfi_offset 17, -8
|
|
; MMR6-NEXT: addu $gp, $2, $25
|
|
; MMR6-NEXT: move $1, $7
|
|
; MMR6-NEXT: lw $7, 60($sp)
|
|
; MMR6-NEXT: lw $17, 64($sp)
|
|
; MMR6-NEXT: lw $3, 68($sp)
|
|
; MMR6-NEXT: move $2, $sp
|
|
; MMR6-NEXT: sw16 $3, 28($2)
|
|
; MMR6-NEXT: sw16 $17, 24($2)
|
|
; MMR6-NEXT: sw16 $7, 20($2)
|
|
; MMR6-NEXT: lw $3, 56($sp)
|
|
; MMR6-NEXT: sw16 $3, 16($2)
|
|
; MMR6-NEXT: lw $25, %call16(__divti3)($gp)
|
|
; MMR6-NEXT: move $7, $1
|
|
; MMR6-NEXT: jalr $25
|
|
; MMR6-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
|
|
; MMR6-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
|
; MMR6-NEXT: addiu $sp, $sp, 40
|
|
; MMR6-NEXT: jrc $ra
|
|
entry:
|
|
%r = sdiv i128 %a, %b
|
|
ret i128 %r
|
|
}
|