677177bb60
Fix issue1: In mips1-4, require a minimum of 2 instructions between a mflo/mfhi and the next mul/dmult/div/ddiv/divu/ddivu instruction. Fix issue2: In mips1-4, should not put mflo into the delay slot for the return. Fix https://github.com/llvm/llvm-project/issues/81291
61 lines
1.8 KiB
LLVM
61 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=mips -mcpu=mips2 -O3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS2
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; RUN: llc < %s -mtriple=mips -mcpu=mips32 -O3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS32
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -O3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS3
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -O3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS64
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define signext i32 @mult_i32(i32 signext %a, i32 signext %b, i32 signext %c) {
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; MIPS2-LABEL: mult_i32:
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; MIPS2: # %bb.0: # %entry
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; MIPS2-NEXT: mult $4, $5
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; MIPS2-NEXT: mflo $1
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; MIPS2-NEXT: nop
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; MIPS2-NEXT: nop
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; MIPS2-NEXT: mult $1, $6
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; MIPS2-NEXT: mflo $2
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; MIPS2-NEXT: jr $ra
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; MIPS2-NEXT: nop
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;
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; MIPS32-LABEL: mult_i32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: mul $1, $4, $5
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: mul $2, $1, $6
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;
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entry:
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%mul = mul nsw i32 %a, %b
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%mul1 = mul nsw i32 %mul, %c
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ret i32 %mul1
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}
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define signext i64 @mul_i64(i64 signext %a, i64 signext %b, i64 signext %c) {
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; MIPS3-LABEL: mul_i64:
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; MIPS3: # %bb.0: # %entry
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; MIPS3-NEXT: dmult $4, $5
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; MIPS3-NEXT: mflo $1
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; MIPS3-NEXT: nop
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; MIPS3-NEXT: nop
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; MIPS3-NEXT: dmult $1, $6
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; MIPS3-NEXT: mflo $2
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; MIPS3-NEXT: jr $ra
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; MIPS3-NEXT: nop
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;
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; MIPS64-LABEL: mul_i64:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: dmult $4, $5
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; MIPS64-NEXT: mflo $1
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; MIPS64-NEXT: dmult $1, $6
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mflo $2
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;
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entry:
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%mul = mul i64 %a, %b
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%mul1 = mul i64 %mul, %c
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ret i64 %mul1
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}
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