674574d25c
Fixes: https://github.com/llvm/llvm-project/issues/71030 Bug only happens in 64bit involving spills. Since we don't know when the spill will happen, all instructions in the chain used to deduce sign extension for eliminating 'extsw' will need to be promoted to 64-bit pseudo instructions. The following instruction will promoted in PPCMIPeepholes: EXTSH, LHA, ISEL to EXTSH8, LHA8, ISEL8
74 lines
2.1 KiB
YAML
74 lines
2.1 KiB
YAML
# RUN: llc -run-pass ppc-mi-peepholes -ppc-eliminate-signext -ppc-eliminate-zeroext -verify-machineinstrs -o - %s | FileCheck %s
|
|
|
|
--- |
|
|
target datalayout = "E-m:e-i64:64-n32:64"
|
|
target triple = "powerpc64le-unknown-linux-gnu"
|
|
define ptr @func(ptr %a) {
|
|
entry:
|
|
ret ptr %a
|
|
}
|
|
|
|
...
|
|
---
|
|
name: func
|
|
alignment: 4
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$x3', virtual-reg: '%0' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 0
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
maxCallFrameSize: 0
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x3
|
|
|
|
; CHECK-LABEL: bb.0.entry:
|
|
; CHECK: %4:g8rc = EXTSW_32_64 killed %3
|
|
; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
|
|
; CHECK: %7:g8rc = EXTSW_32_64 killed %6
|
|
; CHECK: %17:g8rc = INSERT_SUBREG %16, %1, %subreg.sub_32
|
|
; CHECK-NEXT: %18:g8rc = ORIS8 killed %17, 32767
|
|
; CHECK-NEXT: %8:gprc = COPY killed %18.sub_32
|
|
; CHECK: %9:g8rc = INSERT_SUBREG %19, %8, %subreg.sub_32
|
|
; CHECK: %21:g8rc = INSERT_SUBREG %20, %1, %subreg.sub_32
|
|
; CHECK-NEXT: %22:g8rc = ORI8 killed %21, 32768
|
|
; CHECK-NEXT: %10:gprc = COPY killed %22.sub_32
|
|
; CHECK: %11:g8rc = INSERT_SUBREG %23, %10, %subreg.sub_32
|
|
; CHECK: %14:g8rc = COPY killed %13
|
|
|
|
%0:g8rc_nox0 = COPY $x3
|
|
%1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0
|
|
%3:gprc = COPY %2:g8rc_nox0
|
|
%4:g8rc = EXTSW_32_64 %3:gprc ; should not be eliminated
|
|
%5:g8rc = EXTSW_32_64 %1:gprc
|
|
|
|
%6:gprc = ORIS %1:gprc, 32768 ; should not be eliminated
|
|
%7:g8rc = EXTSW_32_64 %6:gprc
|
|
|
|
%8:gprc = ORIS %1:gprc, 32767
|
|
%9:g8rc = EXTSW_32_64 %8:gprc
|
|
|
|
%10:gprc = ORI %1:gprc, 32768
|
|
%11:g8rc = EXTSW_32_64 %10:gprc
|
|
|
|
%12:g8rc = IMPLICIT_DEF
|
|
%13:g8rc = INSERT_SUBREG %12:g8rc, %1:gprc, %subreg.sub_32
|
|
%14:g8rc = RLDICL %13:g8rc, 0, 32
|
|
|
|
...
|