7faf1a0868
This patch adds a pass that provides workarounds for the errata described in GRLIB-TN-0009, GRLIB-TN-0010, GRLIB-TN-0011, GRLIB-TN-0012, and GRLIB-TN-0013, that are applicable to the GR712RC and UT700. The documents are available for download from here: https://www.gaisler.com/index.php/information/app-tech-notes The pass will detect certain sensitive instruction sequences and prevent them from occurring by inserting NOP instruction. Below is an overview of each of the workarounds. A similar implementation is available in GCC. GRLIB-TN-0009: * Insert NOPs to prevent the sequence (stb/sth/st/stf) -> (single non-store/load instruction) -> (any store) * Insert NOPs to prevent the sequence (std/stdf) -> (any store) GRLIB-TN-0010: * Insert a NOP between load instruction and atomic instruction (swap and casa). * Insert a NOP at branch target if load in delay slot and atomic instruction at branch target. * Do not allow functions to begin with atomic instruction. GRLIB-TN-0011: * Insert .p2align 4 before atomic instructions (swap and casa). GRLIB-TN-0012: * Place a NOP at the branch target of an integer branch if it is a floating-point operation or a floating-point branch. GRLIB-TN-0013: * Prevent (div/sqrt) instructions in the delay slot. * Insert NOPs to prevent the sequence (div/sqrt) -> (two or three floating point operations or loads) -> (div/sqrt). * Do not insert NOPs if any of the floating point operations have a dependency on the destination register of the first (div/sqrt). * Do not insert NOPs if one of the floating point operations is a (div/sqrt). * Insert NOPs to prevent (div/sqrt) followed by a branch.
94 lines
1.8 KiB
YAML
94 lines
1.8 KiB
YAML
# RUN: llc %s -mattr=+fix-tn0013 -march=sparc -run-pass=errata-workaround -o - \
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# RUN: | FileCheck %s
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---
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# CHECK: $f0 = FSQRTS $f0
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# CHECK-NEXT: NOP
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# CHECK-NEXT: NOP
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# CHECK-NEXT: $f3 = FADDS $f1, $f2
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# CHECK-NEXT: $f3 = FADDS $f1, $f2
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# CHECK-NEXT: $f0 = FDIVS $f4, $f5
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name: er-8-1
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body: |
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bb.0.entry:
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$f0 = FSQRTS $f0
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$f3 = FADDS $f1, $f2
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$f3 = FADDS $f1, $f2
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$f0 = FDIVS $f4, $f5
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---
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# CHECK: $f0 = FDIVS $f0, $f0
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# CHECK-NEXT: NOP
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# CHECK-NEXT: $f3 = FADDS $f1, $f2
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# CHECK-NEXT: $f3 = FADDS $f1, $f2
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# CHECK-NEXT: $f3 = FADDS $f1, $f2
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# CHECK-NEXT: $f0 = FSQRTS $f4
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name: er-8-2
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body: |
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bb.0.entry:
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$f0 = FDIVS $f0, $f0
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$f3 = FADDS $f1, $f2
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$f3 = FADDS $f1, $f2
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$f3 = FADDS $f1, $f2
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$f0 = FSQRTS $f4
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---
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# CHECK-NOT: NOP
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name: er-9
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body: |
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bb.0.entry:
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$f0 = FSQRTS $f0
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$f3 = FADDS $f1, $f2
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$f3 = FADDS $f0, $f2
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$f3 = FADDS $f1, $f2
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$f0 = FSQRTS $f0
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---
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# CHECK-NOT: NOP
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name: er-10
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body: |
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bb.0.entry:
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$f0 = FSQRTS $f0
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$f4 = FSQRTS $f4
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$f3 = FADDS $f1, $f2
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$f0 = FSQRTS $f0
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---
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# CHECK: er-11
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# CHECK: $f0 = FSQRTS $f0
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# CHECK-NEXT: NOP
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# CHECK: $f0 = FDIVS $f0, $f0
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# CHECK-NEXT: NOP
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name: er-11
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body: |
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bb.0.entry:
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successors: %bb.3, %bb.1
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$f0 = FSQRTS $f0
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FBCOND %bb.3, 22, implicit $fcc0 {
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NOP
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}
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bb.1:
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successors: %bb.3, %bb.4
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$f0 = FDIVS $f0, $f0
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BCOND %bb.4, 10, implicit $icc {
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NOP
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}
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bb.3:
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NOP
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bb.4:
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NOP
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---
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# CHECK: $f1 = FDIVS $f0, $f1
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# CHECK-NEXT: NOP
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# CHECK-NEXT: STri $i6, -84, $i2
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name: er-8-3
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body: |
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bb.0.entry:
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$f1 = FDIVS $f0, $f1
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STri $i6, -84, $i2
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$f0 = LDFri $i6, -84
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$f0 = FITOS $f0
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$f5 = FDIVS $f4, $f0
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...
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