cba70550cc
The "topological" sorting was behaving incorrectly in some cases: the exit of a loop could have a lower rank than a node in the loop. This causes issues when structurizing some patterns, and also codegen issues as we could generate BBs in the incorrect order in regard to the SPIR-V spec. Fixing this ordering alone broke other parts of the structurizer, which by luck worked. Had to fix those. Added more test cases, especially to test basic patterns. I also needed to tweak/disable some tests for 2 reasons: - SPIR-V now required reg2mem/mem2reg to run. Meaning dead stores are optimized away. Some tests require tweaks to avoid having the whole function removed. - Mem2Reg will generate variable & load/stores. This generates G_BITCAST in several cases. And there is currently something wrong we do with G_BITCAST which causes MIR verifier to complain. Until this is resolved, I disabled -verify-machineinstrs flag on those tests. --------- Signed-off-by: Nathan Gauër <brioche@google.com>
292 lines
10 KiB
LLVM
292 lines
10 KiB
LLVM
; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}
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;
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; int process() {
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; int color = 0;
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;
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; int val = 0;
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;
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; if (color < 0) {
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; val = 1;
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; }
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;
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; // for-stmt following if-stmt
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; for (int i = 0; i < 10; ++i) {
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; if (color < 0) { // if-stmt nested in for-stmt
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; val = val + 1;
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; for (int j = 0; j < 15; ++j) { // for-stmt deeply nested in if-then
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; val = val * 2;
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; } // end for (int j
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; val = val + 3;
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; }
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;
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; if (color < 1) { // if-stmt following if-stmt
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; val = val * 4;
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; } else {
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; for (int k = 0; k < 20; ++k) { // for-stmt deeply nested in if-else
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; val = val - 5;
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; if (val < 0) { // deeply nested if-stmt
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; val = val + 100;
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; }
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; } // end for (int k
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; } // end elsek
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; } // end for (int i
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;
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; // if-stmt following for-stmt
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; if (color < 2) {
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; val = val + 6;
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; }
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;
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; return val;
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; }
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;
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; [numthreads(1, 1, 1)]
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; void main() {
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; process();
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; }
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; CHECK: %[[#func_18:]] = OpFunction %[[#uint:]] DontInline %[[#]]
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; CHECK: %[[#bb65:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb66:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb67:]] %[[#bb66:]]
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; CHECK: %[[#bb67:]] = OpLabel
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; CHECK: OpBranch %[[#bb66:]]
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; CHECK: %[[#bb66:]] = OpLabel
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; CHECK: OpBranch %[[#bb68:]]
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; CHECK: %[[#bb68:]] = OpLabel
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; CHECK: OpLoopMerge %[[#bb69:]] %[[#bb70:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb71:]] %[[#bb69:]]
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; CHECK: %[[#bb71:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb72:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb73:]] %[[#bb72:]]
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; CHECK: %[[#bb73:]] = OpLabel
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; CHECK: OpBranch %[[#bb74:]]
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; CHECK: %[[#bb74:]] = OpLabel
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; CHECK: OpLoopMerge %[[#bb75:]] %[[#bb76:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb77:]] %[[#bb75:]]
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; CHECK: %[[#bb77:]] = OpLabel
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; CHECK: OpBranch %[[#bb76:]]
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; CHECK: %[[#bb76:]] = OpLabel
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; CHECK: OpBranch %[[#bb74:]]
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; CHECK: %[[#bb75:]] = OpLabel
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; CHECK: OpBranch %[[#bb72:]]
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; CHECK: %[[#bb72:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb78:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb79:]] %[[#bb80:]]
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; CHECK: %[[#bb79:]] = OpLabel
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; CHECK: OpBranch %[[#bb78:]]
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; CHECK: %[[#bb80:]] = OpLabel
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; CHECK: OpBranch %[[#bb81:]]
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; CHECK: %[[#bb81:]] = OpLabel
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; CHECK: OpLoopMerge %[[#bb82:]] %[[#bb83:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb84:]] %[[#bb82:]]
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; CHECK: %[[#bb84:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb85:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb86:]] %[[#bb85:]]
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; CHECK: %[[#bb86:]] = OpLabel
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; CHECK: OpBranch %[[#bb85:]]
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; CHECK: %[[#bb85:]] = OpLabel
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; CHECK: OpBranch %[[#bb83:]]
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; CHECK: %[[#bb83:]] = OpLabel
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; CHECK: OpBranch %[[#bb81:]]
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; CHECK: %[[#bb82:]] = OpLabel
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; CHECK: OpBranch %[[#bb78:]]
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; CHECK: %[[#bb78:]] = OpLabel
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; CHECK: OpBranch %[[#bb70:]]
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; CHECK: %[[#bb70:]] = OpLabel
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; CHECK: OpBranch %[[#bb68:]]
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; CHECK: %[[#bb69:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb87:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb88:]] %[[#bb87:]]
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; CHECK: %[[#bb88:]] = OpLabel
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; CHECK: OpBranch %[[#bb87:]]
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; CHECK: %[[#bb87:]] = OpLabel
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; CHECK: OpReturnValue %[[#]]
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_61:]] = OpFunction %[[#void:]] DontInline %[[#]]
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; CHECK: %[[#bb89:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_63:]] = OpFunction %[[#void:]] None %[[#]]
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; CHECK: %[[#bb90:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
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target triple = "spirv-unknown-vulkan1.3-compute"
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define spir_func noundef i32 @_Z7processv() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%color = alloca i32, align 4
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%val = alloca i32, align 4
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%i = alloca i32, align 4
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%j = alloca i32, align 4
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%k = alloca i32, align 4
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store i32 0, ptr %color, align 4
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store i32 0, ptr %val, align 4
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%1 = load i32, ptr %color, align 4
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%cmp = icmp slt i32 %1, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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store i32 1, ptr %val, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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store i32 0, ptr %i, align 4
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br label %for.cond
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for.cond: ; preds = %for.inc23, %if.end
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%2 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ]
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%3 = load i32, ptr %i, align 4
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%cmp1 = icmp slt i32 %3, 10
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br i1 %cmp1, label %for.body, label %for.end25
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for.body: ; preds = %for.cond
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%4 = load i32, ptr %color, align 4
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%cmp2 = icmp slt i32 %4, 0
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br i1 %cmp2, label %if.then3, label %if.end8
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if.then3: ; preds = %for.body
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%5 = load i32, ptr %val, align 4
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%add = add nsw i32 %5, 1
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store i32 %add, ptr %val, align 4
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store i32 0, ptr %j, align 4
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br label %for.cond4
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for.cond4: ; preds = %for.inc, %if.then3
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%6 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %2) ]
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%7 = load i32, ptr %j, align 4
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%cmp5 = icmp slt i32 %7, 15
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br i1 %cmp5, label %for.body6, label %for.end
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for.body6: ; preds = %for.cond4
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%8 = load i32, ptr %val, align 4
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%mul = mul nsw i32 %8, 2
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store i32 %mul, ptr %val, align 4
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br label %for.inc
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for.inc: ; preds = %for.body6
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%9 = load i32, ptr %j, align 4
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%inc = add nsw i32 %9, 1
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store i32 %inc, ptr %j, align 4
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br label %for.cond4
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for.end: ; preds = %for.cond4
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%10 = load i32, ptr %val, align 4
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%add7 = add nsw i32 %10, 3
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store i32 %add7, ptr %val, align 4
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br label %if.end8
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if.end8: ; preds = %for.end, %for.body
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%11 = load i32, ptr %color, align 4
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%cmp9 = icmp slt i32 %11, 1
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br i1 %cmp9, label %if.then10, label %if.else
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if.then10: ; preds = %if.end8
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%12 = load i32, ptr %val, align 4
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%mul11 = mul nsw i32 %12, 4
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store i32 %mul11, ptr %val, align 4
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br label %if.end22
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if.else: ; preds = %if.end8
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store i32 0, ptr %k, align 4
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br label %for.cond12
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for.cond12: ; preds = %for.inc19, %if.else
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%13 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %2) ]
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%14 = load i32, ptr %k, align 4
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%cmp13 = icmp slt i32 %14, 20
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br i1 %cmp13, label %for.body14, label %for.end21
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for.body14: ; preds = %for.cond12
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%15 = load i32, ptr %val, align 4
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%sub = sub nsw i32 %15, 5
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store i32 %sub, ptr %val, align 4
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%16 = load i32, ptr %val, align 4
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%cmp15 = icmp slt i32 %16, 0
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br i1 %cmp15, label %if.then16, label %if.end18
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if.then16: ; preds = %for.body14
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%17 = load i32, ptr %val, align 4
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%add17 = add nsw i32 %17, 100
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store i32 %add17, ptr %val, align 4
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br label %if.end18
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if.end18: ; preds = %if.then16, %for.body14
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br label %for.inc19
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for.inc19: ; preds = %if.end18
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%18 = load i32, ptr %k, align 4
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%inc20 = add nsw i32 %18, 1
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store i32 %inc20, ptr %k, align 4
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br label %for.cond12
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for.end21: ; preds = %for.cond12
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br label %if.end22
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if.end22: ; preds = %for.end21, %if.then10
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br label %for.inc23
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for.inc23: ; preds = %if.end22
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%19 = load i32, ptr %i, align 4
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%inc24 = add nsw i32 %19, 1
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store i32 %inc24, ptr %i, align 4
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br label %for.cond
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for.end25: ; preds = %for.cond
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%20 = load i32, ptr %color, align 4
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%cmp26 = icmp slt i32 %20, 2
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br i1 %cmp26, label %if.then27, label %if.end29
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if.then27: ; preds = %for.end25
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%21 = load i32, ptr %val, align 4
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%add28 = add nsw i32 %21, 6
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store i32 %add28, ptr %val, align 4
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br label %if.end29
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if.end29: ; preds = %if.then27, %for.end25
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%22 = load i32, ptr %val, align 4
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ret i32 %22
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}
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare token @llvm.experimental.convergence.entry() #1
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare token @llvm.experimental.convergence.loop() #1
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define internal spir_func void @main() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%call1 = call spir_func noundef i32 @_Z7processv() #3 [ "convergencectrl"(token %0) ]
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ret void
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}
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; Function Attrs: convergent norecurse
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define void @main.1() #2 {
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entry:
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call void @main()
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ret void
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}
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attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #3 = { convergent }
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!llvm.module.flags = !{!0, !1, !2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
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!2 = !{i32 7, !"frame-pointer", i32 2}
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