cba70550cc
The "topological" sorting was behaving incorrectly in some cases: the exit of a loop could have a lower rank than a node in the loop. This causes issues when structurizing some patterns, and also codegen issues as we could generate BBs in the incorrect order in regard to the SPIR-V spec. Fixing this ordering alone broke other parts of the structurizer, which by luck worked. Had to fix those. Added more test cases, especially to test basic patterns. I also needed to tweak/disable some tests for 2 reasons: - SPIR-V now required reg2mem/mem2reg to run. Meaning dead stores are optimized away. Some tests require tweaks to avoid having the whole function removed. - Mem2Reg will generate variable & load/stores. This generates G_BITCAST in several cases. And there is currently something wrong we do with G_BITCAST which causes MIR verifier to complain. Until this is resolved, I disabled -verify-machineinstrs flag on those tests. --------- Signed-off-by: Nathan Gauër <brioche@google.com>
243 lines
7.9 KiB
LLVM
243 lines
7.9 KiB
LLVM
; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}
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;
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; int foo() { return 200; }
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;
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; int process() {
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; int a = 0;
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; int b = 0;
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; int c = 0;
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; const int r = 20;
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; const int s = 40;
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; const int t = 3*r+2*s;
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;
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; switch(int d = 5) {
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; case 1:
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; b += 1;
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; c += foo();
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; case 2:
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; b += 2;
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; break;
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; case 3:
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; {
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; b += 3;
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; break;
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; }
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; case t:
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; b += t;
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; case 4:
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; case 5:
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; b += 5;
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; break;
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; case 6: {
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; case 7:
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; break;}
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; default:
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; break;
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; }
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;
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; return a + b + c;
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; }
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;
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; [numthreads(1, 1, 1)]
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; void main() {
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; process();
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; }
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; CHECK: %[[#func_18:]] = OpFunction %[[#uint:]] DontInline %[[#]]
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; CHECK: %[[#bb52:]] = OpLabel
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; CHECK: OpReturnValue %[[#]]
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_19:]] = OpFunction %[[#uint:]] DontInline %[[#]]
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; CHECK: %[[#bb53:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb54:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb55:]] %[[#bb56:]]
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; CHECK: %[[#bb55:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb57:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb58:]] %[[#bb59:]]
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; CHECK: %[[#bb56:]] = OpLabel
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; CHECK: %[[#bb58:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb60:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb61:]] %[[#bb62:]]
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; CHECK: %[[#bb59:]] = OpLabel
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; CHECK: %[[#bb61:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb63:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb64:]] 1 %[[#bb65:]] 2 %[[#bb63:]] 3 %[[#bb66:]] 140 %[[#bb67:]] 4 %[[#bb68:]] 5 %[[#bb69:]] 6 %[[#bb70:]] 7 %[[#bb71:]]
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; CHECK: %[[#bb62:]] = OpLabel
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; CHECK: %[[#bb64:]] = OpLabel
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; CHECK: OpBranch %[[#bb63:]]
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; CHECK: %[[#bb65:]] = OpLabel
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; CHECK: OpBranch %[[#bb63:]]
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; CHECK: %[[#bb66:]] = OpLabel
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; CHECK: OpBranch %[[#bb63:]]
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; CHECK: %[[#bb67:]] = OpLabel
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; CHECK: OpBranch %[[#bb63:]]
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; CHECK: %[[#bb68:]] = OpLabel
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; CHECK: OpBranch %[[#bb63:]]
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; CHECK: %[[#bb69:]] = OpLabel
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; CHECK: OpBranch %[[#bb63:]]
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; CHECK: %[[#bb70:]] = OpLabel
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; CHECK: OpBranch %[[#bb63:]]
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; CHECK: %[[#bb71:]] = OpLabel
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; CHECK: OpBranch %[[#bb63:]]
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; CHECK: %[[#bb63:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb72:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb73:]] 1 %[[#bb72:]] 2 %[[#bb74:]] 3 %[[#bb75:]]
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; CHECK: %[[#bb73:]] = OpLabel
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; CHECK: OpBranch %[[#bb72:]]
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; CHECK: %[[#bb74:]] = OpLabel
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; CHECK: OpBranch %[[#bb72:]]
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; CHECK: %[[#bb75:]] = OpLabel
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; CHECK: OpBranch %[[#bb72:]]
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; CHECK: %[[#bb72:]] = OpLabel
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; CHECK: OpBranch %[[#bb60:]]
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; CHECK: %[[#bb60:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb76:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb77:]] 1 %[[#bb76:]] 2 %[[#bb78:]]
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; CHECK: %[[#bb77:]] = OpLabel
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; CHECK: OpBranch %[[#bb76:]]
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; CHECK: %[[#bb78:]] = OpLabel
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; CHECK: OpBranch %[[#bb76:]]
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; CHECK: %[[#bb76:]] = OpLabel
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; CHECK: OpBranch %[[#bb57:]]
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; CHECK: %[[#bb57:]] = OpLabel
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; CHECK: OpBranch %[[#bb54:]]
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; CHECK: %[[#bb54:]] = OpLabel
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; CHECK: OpReturnValue %[[#]]
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_48:]] = OpFunction %[[#void:]] DontInline %[[#]]
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; CHECK: %[[#bb79:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_50:]] = OpFunction %[[#void:]] None %[[#]]
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; CHECK: %[[#bb80:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
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target triple = "spirv-unknown-vulkan1.3-compute"
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define spir_func noundef i32 @_Z3foov() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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ret i32 200
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}
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare token @llvm.experimental.convergence.entry() #1
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define spir_func noundef i32 @_Z7processv() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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%r = alloca i32, align 4
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%s = alloca i32, align 4
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%t = alloca i32, align 4
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%d = alloca i32, align 4
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store i32 0, ptr %a, align 4
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store i32 0, ptr %b, align 4
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store i32 0, ptr %c, align 4
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store i32 20, ptr %r, align 4
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store i32 40, ptr %s, align 4
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store i32 140, ptr %t, align 4
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store i32 5, ptr %d, align 4
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%1 = load i32, ptr %d, align 4
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switch i32 %1, label %sw.default [
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i32 1, label %sw.bb
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i32 2, label %sw.bb3
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i32 3, label %sw.bb5
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i32 140, label %sw.bb7
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i32 4, label %sw.bb9
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i32 5, label %sw.bb9
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i32 6, label %sw.bb11
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i32 7, label %sw.bb12
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]
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sw.bb: ; preds = %entry
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%2 = load i32, ptr %b, align 4
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%add = add nsw i32 %2, 1
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store i32 %add, ptr %b, align 4
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%call1 = call spir_func noundef i32 @_Z3foov() #3 [ "convergencectrl"(token %0) ]
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%3 = load i32, ptr %c, align 4
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%add2 = add nsw i32 %3, %call1
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store i32 %add2, ptr %c, align 4
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br label %sw.bb3
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sw.bb3: ; preds = %entry, %sw.bb
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%4 = load i32, ptr %b, align 4
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%add4 = add nsw i32 %4, 2
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store i32 %add4, ptr %b, align 4
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br label %sw.epilog
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sw.bb5: ; preds = %entry
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%5 = load i32, ptr %b, align 4
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%add6 = add nsw i32 %5, 3
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store i32 %add6, ptr %b, align 4
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br label %sw.epilog
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sw.bb7: ; preds = %entry
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%6 = load i32, ptr %b, align 4
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%add8 = add nsw i32 %6, 140
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store i32 %add8, ptr %b, align 4
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br label %sw.bb9
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sw.bb9: ; preds = %entry, %entry, %sw.bb7
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%7 = load i32, ptr %b, align 4
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%add10 = add nsw i32 %7, 5
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store i32 %add10, ptr %b, align 4
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br label %sw.epilog
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sw.bb11: ; preds = %entry
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br label %sw.bb12
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sw.bb12: ; preds = %entry, %sw.bb11
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br label %sw.epilog
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sw.default: ; preds = %entry
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br label %sw.epilog
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sw.epilog: ; preds = %sw.default, %sw.bb12, %sw.bb9, %sw.bb5, %sw.bb3
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%8 = load i32, ptr %a, align 4
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%9 = load i32, ptr %b, align 4
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%add13 = add nsw i32 %8, %9
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%10 = load i32, ptr %c, align 4
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%add14 = add nsw i32 %add13, %10
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ret i32 %add14
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}
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define internal spir_func void @main() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%call1 = call spir_func noundef i32 @_Z7processv() #3 [ "convergencectrl"(token %0) ]
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ret void
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}
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; Function Attrs: convergent norecurse
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define void @main.1() #2 {
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entry:
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call void @main()
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ret void
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}
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attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #3 = { convergent }
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!llvm.module.flags = !{!0, !1, !2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
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!2 = !{i32 7, !"frame-pointer", i32 2}
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