a21abc782a
This is an attempt at rebooting https://reviews.llvm.org/D28990 I've included AutoUpgrade changes to modify the data layout to satisfy the compatible layout check. But this does mean alloca, loads, stores, etc in old IR will automatically get this new alignment. This should fix PR46320. Reviewed By: echristo, rnk, tmgross Differential Revision: https://reviews.llvm.org/D86310
422 lines
12 KiB
LLVM
422 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i686-windows < %s | FileCheck %s
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declare void @addrof_i1(ptr)
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declare void @addrof_i32(ptr)
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declare void @addrof_i64(ptr)
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declare void @addrof_i128(ptr)
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declare void @addrof_i32_x3(ptr, ptr, ptr)
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define void @simple(i32 %x) {
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; CHECK-LABEL: simple:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: retl
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entry:
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%x.addr = alloca i32
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store i32 %x, ptr %x.addr
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call void @addrof_i32(ptr %x.addr)
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ret void
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}
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; We need to load %x before calling addrof_i32 now because it could mutate %x in
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; place.
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define i32 @use_arg(i32 %x) {
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; CHECK-LABEL: use_arg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: retl
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entry:
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%x.addr = alloca i32
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store i32 %x, ptr %x.addr
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call void @addrof_i32(ptr %x.addr)
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ret i32 %x
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}
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; We won't copy elide for types needing legalization such as i64 or i1.
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define i64 @split_i64(i64 %x) {
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; CHECK-LABEL: split_i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %edi
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i64
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: movl %edi, %edx
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: popl %edi
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; CHECK-NEXT: retl
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entry:
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%x.addr = alloca i64, align 4
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store i64 %x, ptr %x.addr, align 4
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call void @addrof_i64(ptr %x.addr)
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ret i64 %x
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}
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define i1 @i1_arg(i1 %x) {
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; CHECK-LABEL: i1_arg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushl %ebx
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %ebx
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; CHECK-NEXT: movl %ebx, %eax
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; CHECK-NEXT: andb $1, %al
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; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp)
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i1
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: movl %ebx, %eax
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: popl %ebx
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; CHECK-NEXT: retl
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%x.addr = alloca i1
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store i1 %x, ptr %x.addr
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call void @addrof_i1(ptr %x.addr)
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ret i1 %x
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}
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; We can't copy elide when an i64 is split between registers and memory in a
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; fastcc function.
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define fastcc i64 @fastcc_split_i64(ptr %p, i64 %x) {
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; CHECK-LABEL: fastcc_split_i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %edi
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: movl %edx, %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
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; CHECK-NEXT: movl %edi, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %edx, (%esp)
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; CHECK-NEXT: movl %esp, %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i64
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: movl %edi, %edx
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; CHECK-NEXT: addl $8, %esp
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: popl %edi
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; CHECK-NEXT: retl
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entry:
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%x.addr = alloca i64, align 4
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store i64 %x, ptr %x.addr, align 4
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call void @addrof_i64(ptr %x.addr)
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ret i64 %x
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}
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; We can't copy elide when it would reduce the user requested alignment.
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define void @high_alignment(i32 %x) {
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; CHECK-LABEL: high_alignment:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %ebp
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; CHECK-NEXT: movl %esp, %ebp
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; CHECK-NEXT: andl $-128, %esp
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; CHECK-NEXT: subl $128, %esp
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; CHECK-NEXT: movl 8(%ebp), %eax
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; CHECK-NEXT: movl %eax, (%esp)
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; CHECK-NEXT: movl %esp, %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: movl %ebp, %esp
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; CHECK-NEXT: popl %ebp
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; CHECK-NEXT: retl
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entry:
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%x.p = alloca i32, align 128
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store i32 %x, ptr %x.p
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call void @addrof_i32(ptr %x.p)
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ret void
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}
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; We can't copy elide when it would reduce the ABI required alignment.
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; FIXME: We should lower the ABI alignment of i64 on Windows, since MSVC
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; doesn't guarantee it.
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define void @abi_alignment(i64 %x) {
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; CHECK-LABEL: abi_alignment:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %ebp
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; CHECK-NEXT: movl %esp, %ebp
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; CHECK-NEXT: andl $-8, %esp
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: movl 8(%ebp), %eax
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; CHECK-NEXT: movl 12(%ebp), %ecx
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; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %eax, (%esp)
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; CHECK-NEXT: movl %esp, %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i64
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: movl %ebp, %esp
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; CHECK-NEXT: popl %ebp
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; CHECK-NEXT: retl
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entry:
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%x.p = alloca i64
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store i64 %x, ptr %x.p
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call void @addrof_i64(ptr %x.p)
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ret void
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}
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; The code we generate for this is unimportant. This is mostly a crash test.
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define void @split_i128(ptr %sret, i128 %x) {
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; CHECK-LABEL: split_i128:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %ebp
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; CHECK-NEXT: movl %esp, %ebp
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; CHECK-NEXT: pushl %ebx
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; CHECK-NEXT: pushl %edi
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: andl $-16, %esp
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; CHECK-NEXT: subl $48, %esp
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; CHECK-NEXT: movl 12(%ebp), %eax
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; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: movl 16(%ebp), %ebx
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; CHECK-NEXT: movl 20(%ebp), %esi
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; CHECK-NEXT: movl 24(%ebp), %edi
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; CHECK-NEXT: movl %edi, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %esi, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %ebx, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i128
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: movl 8(%ebp), %eax
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; CHECK-NEXT: movl %edi, 12(%eax)
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; CHECK-NEXT: movl %esi, 8(%eax)
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; CHECK-NEXT: movl %ebx, 4(%eax)
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; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
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; CHECK-NEXT: movl %ecx, (%eax)
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; CHECK-NEXT: leal -12(%ebp), %esp
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: popl %edi
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; CHECK-NEXT: popl %ebx
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; CHECK-NEXT: popl %ebp
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; CHECK-NEXT: retl
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entry:
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%x.addr = alloca i128
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store i128 %x, ptr %x.addr
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call void @addrof_i128(ptr %x.addr)
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store i128 %x, ptr %sret
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ret void
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}
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; Check that we load all of x, y, and z before the call.
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define i32 @three_args(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: three_args:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: addl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: addl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: pushl %ecx
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; CHECK-NEXT: pushl %edx
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; CHECK-NEXT: calll _addrof_i32_x3
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; CHECK-NEXT: addl $12, %esp
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: retl
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entry:
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%z.addr = alloca i32, align 4
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%y.addr = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %z, ptr %z.addr, align 4
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store i32 %y, ptr %y.addr, align 4
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store i32 %x, ptr %x.addr, align 4
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call void @addrof_i32_x3(ptr %x.addr, ptr %y.addr, ptr %z.addr)
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%s1 = add i32 %x, %y
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%sum = add i32 %s1, %z
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ret i32 %sum
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}
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define void @two_args_same_alloca(i32 %x, i32 %y) {
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; CHECK-LABEL: two_args_same_alloca:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: retl
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entry:
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%x.addr = alloca i32
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store i32 %x, ptr %x.addr
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store i32 %y, ptr %x.addr
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call void @addrof_i32(ptr %x.addr)
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ret void
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}
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define void @avoid_byval(ptr byval(i32) %x) {
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; CHECK-LABEL: avoid_byval:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, (%esp)
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: popl %eax
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; CHECK-NEXT: retl
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entry:
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%x.p.p = alloca ptr
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store ptr %x, ptr %x.p.p
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call void @addrof_i32(ptr %x)
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ret void
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}
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define void @avoid_inalloca(ptr inalloca(i32) %x) {
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; CHECK-LABEL: avoid_inalloca:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, (%esp)
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: popl %eax
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; CHECK-NEXT: retl
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entry:
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%x.p.p = alloca ptr
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store ptr %x, ptr %x.p.p
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call void @addrof_i32(ptr %x)
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ret void
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}
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define void @avoid_preallocated(ptr preallocated(i32) %x) {
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; CHECK-LABEL: avoid_preallocated:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, (%esp)
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: popl %eax
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; CHECK-NEXT: retl
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entry:
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%x.p.p = alloca ptr
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store ptr %x, ptr %x.p.p
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call void @addrof_i32(ptr %x)
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ret void
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}
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; Don't elide the copy when the alloca is escaped with a store.
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define void @escape_with_store(i32 %x) {
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; CHECK-LABEL: escape_with_store:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %esp, %ecx
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; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %eax, (%esp)
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; CHECK-NEXT: pushl %ecx
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $12, %esp
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; CHECK-NEXT: retl
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%x1 = alloca i32
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%x2 = alloca ptr
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store ptr %x1, ptr %x2
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%x3 = load ptr, ptr %x2
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store i32 0, ptr %x3
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store i32 %x, ptr %x1
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call void @addrof_i32(ptr %x1)
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ret void
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}
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; This test case exposed issues with the use of TokenFactor.
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define void @sret_and_elide(ptr sret(i32) %sret, i32 %v) {
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; CHECK-LABEL: sret_and_elide:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushl %edi
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: movl %edi, (%esi)
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: popl %edi
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; CHECK-NEXT: retl
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%v.p = alloca i32
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store i32 %v, ptr %v.p
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call void @addrof_i32(ptr %v.p)
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store i32 %v, ptr %sret
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ret void
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}
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define void @avoid_partially_initialized_alloca(i32 %x) {
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; CHECK-LABEL: avoid_partially_initialized_alloca:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushl %ebp
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; CHECK-NEXT: movl %esp, %ebp
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; CHECK-NEXT: andl $-8, %esp
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: movl 8(%ebp), %eax
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; CHECK-NEXT: movl %eax, (%esp)
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; CHECK-NEXT: movl %esp, %eax
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: calll _addrof_i32
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; CHECK-NEXT: addl $4, %esp
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; CHECK-NEXT: movl %ebp, %esp
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; CHECK-NEXT: popl %ebp
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; CHECK-NEXT: retl
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%a = alloca i64
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store i32 %x, ptr %a
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call void @addrof_i32(ptr %a)
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ret void
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}
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; Ensure no copy elision happens as the two i3 values fed into icmp may have
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; garbage in the upper bits, a truncation is needed.
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define i1 @use_i3(i3 %a1, i3 %a2) {
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; CHECK-LABEL: use_i3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: andb $7, %al
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; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: andb $7, %cl
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; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp)
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; CHECK-NEXT: cmpb %cl, %al
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: popl %ecx
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; CHECK-NEXT: retl
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%tmp = alloca i3
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store i3 %a2, ptr %tmp
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%val = load i3, ptr %tmp
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%res = icmp eq i3 %a1, %val
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ret i1 %res
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}
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