4b1b51ac52
Enables initial non-power-of-2 support (but still requires number of elements, forming whole registers) for reductions. Enables extra vectorization for MultiSource/Benchmarks/7zip/7zip-benchmark, CINT2006/464.h264ref and CFP2017rate/526.blender_r (checked for SSE2) Reviewers: RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/112361
54 lines
2.6 KiB
LLVM
54 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=aarch64-unknown-unknown | FileCheck %s
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; This test is reduced from the TSVC evaluation of vectorizers:
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; https://github.com/llvm/llvm-test-suite/commits/main/MultiSource/Benchmarks/TSVC/LoopRerolling-flt/tsc.c
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; FIXME
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; This test is currently getting vectorized with VF=2. We should be able
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; to vectorize it with VF=4. Specifically, we should be able to have 1 load of
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; <4 x float> instead of 2 loads of <2 x float>, and there should be no need
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; for shufflevectors.
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; The current issue comes from the Left-Hand-Side fmul operands.
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; These operands are coming from 4 loads which are not
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; contiguous. The score estimation needs to be corrected, so that these 4 loads
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; are not selected for vectorization. Instead we should vectorize with
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; contiguous loads, from %a plus offsets 0 to 3, or offsets 1 to 4.
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define void @s116_modified(ptr %a) {
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; CHECK-LABEL: @s116_modified(
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; CHECK-NEXT: [[A:%.*]] = getelementptr inbounds float, ptr [[GEP1:%.*]], i64 2
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; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds float, ptr [[GEP1]], i64 3
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; CHECK-NEXT: [[LD0:%.*]] = load float, ptr [[A]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[GEP1]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[GEP3]], align 4
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[LD0]], i32 1
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; CHECK-NEXT: [[TMP6:%.*]] = call <4 x float> @llvm.vector.insert.v4f32.v2f32(<4 x float> [[TMP5]], <2 x float> [[TMP2]], i64 2)
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; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP6]], <4 x i32> <i32 1, i32 1, i32 5, i32 6>
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; CHECK-NEXT: [[TMP8:%.*]] = fmul fast <4 x float> [[TMP6]], [[TMP7]]
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; CHECK-NEXT: store <4 x float> [[TMP8]], ptr [[GEP1]], align 4
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; CHECK-NEXT: ret void
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;
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%gep1 = getelementptr inbounds float, ptr %a, i64 1
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%gep2 = getelementptr inbounds float, ptr %a, i64 2
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%gep3 = getelementptr inbounds float, ptr %a, i64 3
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%gep4 = getelementptr inbounds float, ptr %a, i64 4
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%ld0 = load float, ptr %a
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%ld1 = load float, ptr %gep1
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%ld2 = load float, ptr %gep2
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%ld3 = load float, ptr %gep3
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%ld4 = load float, ptr %gep4
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%mul0 = fmul fast float %ld0, %ld1
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%mul1 = fmul fast float %ld2, %ld1
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%mul2 = fmul fast float %ld3, %ld2
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%mul3 = fmul fast float %ld4, %ld3
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store float %mul0, ptr %a
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store float %mul1, ptr %gep1
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store float %mul2, ptr %gep2
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store float %mul3, ptr %gep3
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ret void
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}
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