This patch rewrites the ArmSME tile allocator to use liveness information to make better tile allocation decisions and improve the correctness of the ArmSME dialect. This algorithm used here is a linear scan over live ranges, where live ranges are assigned to tiles as they appear in the program (chronologically). Live ranges release their assigned tile ID when the current program point is passed their end. This is a greedy algorithm (which is mainly to keep the implementation relatively straightforward), and because it seems to be sufficient for most kernels (e.g. matmuls) that use ArmSME. The general steps of this are roughly from https://link.springer.com/content/pdf/10.1007/3-540-45937-5_17.pdf, though there have been a few simplifications and assumptions made for our use case. Hopefully, the only changes needed for a user of the ArmSME dialect is that: - `-allocate-arm-sme-tiles` will no longer be a standalone pass - `-test-arm-sme-tile-allocation` is only for unit tests - `-convert-arm-sme-to-llvm` must happen after `-convert-scf-to-cf` - SME tile allocation is now part of the LLVM conversion By integrating this into the `ArmSME -> LLVM` conversion we can allow high-level (value-based) ArmSME operations to be side-effect-free, as we can guarantee nothing will rearrange ArmSME operations before we emit intrinsics (which could invalidate the tile allocation). The hope is for ArmSME operations to have no hidden state/side effects and allow easily lowering dialects such as `vector` and `arith` to SME, without making assumptions about how the input IR looks, as the semantics of the operations will be the same. That is no (new) side effects and the IR follows the rules of SSA (a value will never change). The aim is correctness, so we have a base for working on optimizations.
173 lines
5.9 KiB
C++
173 lines
5.9 KiB
C++
//===- Utils.cpp - Utilities to support the ArmSME dialect ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements utilities for the ArmSME dialect.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/ArmSME/Utils/Utils.h"
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#include "mlir/Dialect/ArmSME/IR/ArmSME.h"
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namespace mlir::arm_sme {
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unsigned getSMETileSliceMinNumElts(Type type) {
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assert(isValidSMETileElementType(type) && "invalid tile type!");
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return MinStreamingVectorLengthInBits / type.getIntOrFloatBitWidth();
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}
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bool isValidSMETileElementType(Type type) {
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return type.isInteger(8) || type.isInteger(16) || type.isInteger(32) ||
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type.isInteger(64) || type.isInteger(128) || type.isF16() ||
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type.isBF16() || type.isF32() || type.isF64() || type.isF128();
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}
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bool isValidSMETileVectorType(VectorType vType) {
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if ((vType.getRank() != 2) || !vType.allDimsScalable())
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return false;
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auto elemType = vType.getElementType();
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if (!isValidSMETileElementType(elemType))
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return false;
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unsigned minNumElts = getSMETileSliceMinNumElts(elemType);
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if (vType.getShape() != ArrayRef<int64_t>({minNumElts, minNumElts}))
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return false;
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return true;
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}
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std::optional<ArmSMETileType> getSMETileType(VectorType type) {
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if (!isValidSMETileVectorType(type))
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return {};
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switch (type.getElementTypeBitWidth()) {
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case 8:
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return ArmSMETileType::ZAB;
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case 16:
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return ArmSMETileType::ZAH;
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case 32:
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return ArmSMETileType::ZAS;
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case 64:
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return ArmSMETileType::ZAD;
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case 128:
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return ArmSMETileType::ZAQ;
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default:
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llvm_unreachable("unknown SME tile type");
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}
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}
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LogicalResult verifyOperationHasValidTileId(Operation *op) {
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auto tileOp = llvm::dyn_cast<ArmSMETileOpInterface>(op);
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if (!tileOp)
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return success(); // Not a tile op (no need to check).
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auto tileId = tileOp.getTileId();
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if (!tileId)
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return success(); // Not having a tile ID (yet) is okay.
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if (!tileId.getType().isSignlessInteger(32))
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return tileOp.emitOpError("tile ID should be a 32-bit signless integer");
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return success();
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}
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scf::ForOp createLoopOverTileSlices(
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PatternRewriter &rewriter, Location loc, Value initTile,
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std::function<Value(OpBuilder &, Location, Value, Value)> makeLoopBody) {
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OpBuilder::InsertionGuard g(rewriter);
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auto step = rewriter.create<arith::ConstantIndexOp>(loc, 1);
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auto minTileSlices = rewriter.create<arith::ConstantIndexOp>(
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loc, llvm::cast<VectorType>(initTile.getType()).getDimSize(0));
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auto vscale =
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rewriter.create<vector::VectorScaleOp>(loc, rewriter.getIndexType());
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auto lowerBound = rewriter.create<arith::ConstantIndexOp>(loc, 0);
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auto numTileSlices =
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rewriter.create<arith::MulIOp>(loc, minTileSlices, vscale);
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auto forOp = rewriter.create<scf::ForOp>(loc, lowerBound, numTileSlices, step,
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ValueRange{initTile});
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rewriter.setInsertionPointToStart(forOp.getBody());
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Value nextTile =
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makeLoopBody(rewriter, loc, /*tileSliceIndex=*/forOp.getInductionVar(),
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/*currentTile=*/forOp.getRegionIterArg(0));
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rewriter.create<scf::YieldOp>(loc, nextTile);
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return forOp;
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}
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bool isMultipleOfSMETileVectorType(VectorType vType) {
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if (vType.getRank() != 2 || !vType.allDimsScalable())
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return false;
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auto elementType = vType.getElementType();
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if (!isValidSMETileElementType(elementType))
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return false;
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unsigned minNumElts = getSMETileSliceMinNumElts(elementType);
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int64_t vectorRows = vType.getDimSize(0);
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int64_t vectorCols = vType.getDimSize(1);
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return (vectorRows > minNumElts || vectorCols > minNumElts) &&
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vectorRows % minNumElts == 0 && vectorCols % minNumElts == 0;
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}
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VectorType getSMETileTypeForElement(Type elementType) {
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unsigned minNumElts = getSMETileSliceMinNumElts(elementType);
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return VectorType::get({minNumElts, minNumElts}, elementType, {true, true});
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}
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void eraseTriviallyDeadTileOps(IRRewriter &rewriter,
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FunctionOpInterface function) {
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SmallVector<Operation *> worklist;
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function->walk([&](Operation *op) {
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auto armSMEOp = dyn_cast<arm_sme::ArmSMETileOpInterface>(op);
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if (armSMEOp && isOpTriviallyDead(armSMEOp))
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worklist.push_back(armSMEOp);
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});
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while (!worklist.empty()) {
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Operation *op = worklist.pop_back_val();
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if (!isOpTriviallyDead(op))
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continue;
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for (Value value : op->getOperands()) {
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if (auto armSMEOp = value.getDefiningOp<arm_sme::ArmSMETileOpInterface>())
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worklist.push_back(armSMEOp);
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}
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rewriter.eraseOp(op);
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}
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}
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bool isTriviallyCloneableTileOp(arm_sme::ArmSMETileOpInterface tileOp) {
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return tileOp && tileOp->getNumResults() == 1 &&
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tileOp->getNumOperands() == 0 && isPure(tileOp);
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}
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bool hasTileResult(arm_sme::ArmSMETileOpInterface tileOp) {
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for (Value result : tileOp->getResults()) {
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if (arm_sme::isValidSMETileVectorType(result.getType()))
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return true;
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}
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return false;
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}
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OpOperand *getTileOpOperand(arm_sme::ArmSMETileOpInterface tileOp) {
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if (!tileOp)
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return nullptr;
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auto isTileOperandType = [](OpOperand &operand) {
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return arm_sme::isValidSMETileVectorType(operand.get().getType());
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};
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assert(llvm::count_if(tileOp->getOpOperands(), isTileOperandType) <= 1 &&
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"expected at most one tile operand");
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OpOperand *tileOperand =
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llvm::find_if(tileOp->getOpOperands(), isTileOperandType);
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if (tileOperand == tileOp->getOpOperands().end())
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return nullptr;
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return tileOperand;
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}
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bool isTileTypeGreaterOrEqual(ArmSMETileType typeA, ArmSMETileType typeB) {
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// Note: This is <= due to how tile types are numbered in ArmSMEOps.td.
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return static_cast<unsigned>(typeA) <= static_cast<unsigned>(typeB);
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}
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} // namespace mlir::arm_sme
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