08906a3c62
It's possible to have a use of the private resource descriptor or scratch wave offset registers even though there are no allocated stack objects. This would result in continuing to use the maximum number reserved registers. This could go over the number of SGPRs available on VI, or violate the SGPR limit requested by the function attributes. llvm-svn: 285435
123 lines
4.6 KiB
LLVM
123 lines
4.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}max_14_sgprs:
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; FIXME: Should be ablo to skip this copying of the private segment
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; buffer because all the SGPR spills are to VGPRs.
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; CHECK: s_mov_b64 s[6:7], s[2:3]
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; CHECK: s_mov_b64 s[4:5], s[0:1]
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; CHECK: SGPRBlocks: 1
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; CHECK: NumSGPRsForWavesPerEU: 14
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define void @max_14_sgprs(i32 addrspace(1)* %out1,
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i32 addrspace(1)* %out2,
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i32 addrspace(1)* %out3,
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i32 addrspace(1)* %out4,
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i32 %one, i32 %two, i32 %three, i32 %four) #0 {
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store i32 %one, i32 addrspace(1)* %out1
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store i32 %two, i32 addrspace(1)* %out2
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store i32 %three, i32 addrspace(1)* %out3
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store i32 %four, i32 addrspace(1)* %out4
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ret void
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}
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; private resource: 4
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; scratch wave offset: 1
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; workgroup ids: 3
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; dispatch id: 2
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; queue ptr: 2
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; flat scratch init: 2
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; ---------------------
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; total: 14
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; + reserved vcc, flat_scratch = 18
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; Because we can't handle re-using the last few input registers as the
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; special vcc etc. registers (as well as decide to not use the unused
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; features when the number of registers is frozen), this ends up using
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; more than expected.
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; ALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs:
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; TOSGPR: SGPRBlocks: 2
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; TOSGPR: NumSGPRsForWavesPerEU: 18
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; TOSMEM: s_mov_b64 s[6:7], s[2:3]
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; TOSMEM: s_mov_b32 s9, s13
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; TOSMEM: s_mov_b64 s[4:5], s[0:1]
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; TOSMEM: SGPRBlocks: 2
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; TOSMEM: NumSGPRsForWavesPerEU: 18
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define void @max_12_sgprs_14_input_sgprs(i32 addrspace(1)* %out1,
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i32 addrspace(1)* %out2,
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i32 addrspace(1)* %out3,
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i32 addrspace(1)* %out4,
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i32 %one, i32 %two, i32 %three, i32 %four) #2 {
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store volatile i32 0, i32* undef
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%x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %x.0, i32 addrspace(1)* undef
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%x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %x.0, i32 addrspace(1)* undef
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%x.2 = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %x.0, i32 addrspace(1)* undef
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%x.3 = call i64 @llvm.amdgcn.dispatch.id()
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store volatile i64 %x.3, i64 addrspace(1)* undef
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%x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef
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%x.5 = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr()
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store volatile i8 addrspace(2)* %x.5, i8 addrspace(2)* addrspace(1)* undef
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store i32 %one, i32 addrspace(1)* %out1
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store i32 %two, i32 addrspace(1)* %out2
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store i32 %three, i32 addrspace(1)* %out3
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store i32 %four, i32 addrspace(1)* %out4
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ret void
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}
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; ALL-LABEL: max_12_sgprs_12_input_sgprs{{$}}
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; ; Make sure copies for input buffer are not clobbered. This requires
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; ; swapping the order the registers are copied from what normally
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; ; happens.
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; TOSMEM: s_mov_b64 s[6:7], s[2:3]
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; TOSMEM: s_mov_b64 s[4:5], s[0:1]
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; TOSMEM: s_mov_b32 s3, s11
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; ALL: SGPRBlocks: 1
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; ALL: NumSGPRsForWavesPerEU: 16
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define void @max_12_sgprs_12_input_sgprs(i32 addrspace(1)* %out1,
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i32 addrspace(1)* %out2,
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i32 addrspace(1)* %out3,
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i32 addrspace(1)* %out4,
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i32 %one, i32 %two, i32 %three, i32 %four) #2 {
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store volatile i32 0, i32* undef
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%x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %x.0, i32 addrspace(1)* undef
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%x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %x.0, i32 addrspace(1)* undef
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%x.2 = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %x.0, i32 addrspace(1)* undef
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%x.3 = call i64 @llvm.amdgcn.dispatch.id()
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store volatile i64 %x.3, i64 addrspace(1)* undef
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%x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef
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store i32 %one, i32 addrspace(1)* %out1
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store i32 %two, i32 addrspace(1)* %out2
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store i32 %three, i32 addrspace(1)* %out3
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store i32 %four, i32 addrspace(1)* %out4
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ret void
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}
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declare i32 @llvm.amdgcn.workgroup.id.x() #1
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declare i32 @llvm.amdgcn.workgroup.id.y() #1
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declare i32 @llvm.amdgcn.workgroup.id.z() #1
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declare i64 @llvm.amdgcn.dispatch.id() #1
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declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #1
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declare i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #1
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attributes #0 = { nounwind "amdgpu-num-sgpr"="14" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "amdgpu-num-sgpr"="12" }
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attributes #3 = { nounwind "amdgpu-num-sgpr"="11" }
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