Matt Arsenault 4d42e8b5d1 Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting" ...

This reverts commit a496c8be6e.

The workaround in c26dfc81e2 should work
around the underlying problem with SUBREG_TO_REG.

2023-07-31 20:15:45 -04:00

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custom-pseudo-source-values.ll

[AMDGPU] Use resource base for buffer instruction MachineMemOperands

2023-06-05 17:06:57 +00:00

dead-flag-on-use-operand-parse-error.mir

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empty-custom-regmask.mir

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expected-target-index-name.mir

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extra-imm-operand.mir

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extra-reg-operand.mir

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intrinsics.mir

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invalid-frame-index2.mir

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invalid-frame-index-invalid-fixed-stack.mir

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invalid-frame-index-invalid-stack.mir

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invalid-frame-index-no-stack.mir

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invalid-frame-index.mir

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invalid-target-index-operand.mir

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killed-flag-on-def-parse-error.mir

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lit.local.cfg

[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm

2023-05-17 17:03:15 +02:00

llc-target-cpu-attr-from-cmdline-ir.mir

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llc-target-cpu-attr-from-cmdline.mir

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long-branch-reg-all-sgpr-used.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-after-pei.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-dynlds-align-invalid-case.mir

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machine-function-info-long-branch-reg-debug.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-long-branch-reg.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-no-ir.mir

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-register-parse-error1.mir

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machine-function-info-register-parse-error2.mir

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machine-function-info.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-metadata-error.mir

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machine-metadata.mir

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mfi-frame-offset-reg-class.mir

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mfi-parse-error-frame-offset-reg.mir

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mfi-parse-error-scratch-rsrc-reg.mir

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mfi-parse-error-stack-ptr-offset-reg.mir

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mfi-scratch-rsrc-reg-reg-class.mir

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mfi-stack-ptr-offset-reg-class.mir

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mir-canon-multi.mir

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mircanon-memoperands.mir

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parse-order-reserved-regs.mir

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sgpr-for-exec-copy-invalid-reg.mir

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

stack-id-assert.mir

Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"

2023-07-31 20:15:45 -04:00

stack-id.mir

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subreg-def-is-not-ssa.mir

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syncscopes.mir

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target-flags.mir

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target-index-operands.mir

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target-memoperands.mir

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vgpr-for-agpr-copy-invalid-reg.mir

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virtreg-uses-unallocatable-class.mir

[Support] Implement LLVM_ENABLE_REVERSE_ITERATION for StringMap

2023-07-21 08:46:51 -07:00

wwm-reserved-regs-invalid-reg.mir

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wwm-reserved-regs-not-a-reg.mir

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wwm-reserved-regs.mir

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