Craig Topper 8ed046fc15 [RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb. ...

While working on -riscv-experimental-rv64-legal-i32, I noticed this
missed optimization in our current codegen.

This expands to SADDO/SSUBO+select while still in i32. These will
be type legalized individually.

2024-02-04 23:15:58 -08:00

..

AsmParser

[RISCV] Support TLSDESC in the RISC-V backend (#66915)

2024-01-23 16:16:07 -08:00

Disassembler

[RISCV] Re-implement Zacas MC layer support to make it usable for CodeGen. (#77418)

2024-01-10 09:18:40 -08:00

GISel

[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)

2024-02-01 15:06:43 -05:00

MCA

[RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (#76869)

2024-01-04 15:40:30 -05:00

MCTargetDesc

[RISCV] Remove StackAlign attribute enum. NFC (#79946)

2024-01-30 09:38:24 -08:00

TargetInfo

…

CMakeLists.txt

[RISCV] Use TableGen-based macro fusion (#72224)

2024-01-25 17:10:49 +08:00

RISCV.h

[Target] Remove unused forward declarations (NFC)

2023-12-10 10:38:55 -08:00

RISCV.td

[RISCV] Use TableGen-based macro fusion (#72224)

2024-01-25 17:10:49 +08:00

RISCVAsmPrinter.cpp

[RISCV] Support TLSDESC in the RISC-V backend (#66915)

2024-01-23 16:16:07 -08:00

RISCVCallingConv.td

[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)

2024-01-16 20:44:30 +08:00

RISCVCodeGenPrepare.cpp

[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.

2024-01-19 14:44:47 -08:00

RISCVCombine.td

…

RISCVDeadRegisterDefinitions.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVExpandAtomicPseudoInsts.cpp

…

RISCVExpandPseudoInsts.cpp

[RISCV] Support TLSDESC in the RISC-V backend (#66915)

2024-01-23 16:16:07 -08:00

RISCVFeatures.td

[RISCV] Rename some SubtargetFeature names to remove an extra 's'. NFC

2024-02-02 15:49:06 -08:00

RISCVFoldMasks.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVFrameLowering.cpp

[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)

2024-01-16 20:44:30 +08:00

RISCVFrameLowering.h

[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)

2024-01-16 20:44:30 +08:00

RISCVGatherScatterLowering.cpp

[RISCV] Don't check haveNoCommonBitsSet in RISCVGatherScatterLowering

2024-01-15 14:09:52 +07:00

RISCVGISel.td

[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (#72825)

2023-12-04 13:00:34 -08:00

RISCVInsertReadWriteCSR.cpp

[RISCV] Implement foward inserting save/restore FRM instructions. (#77744)

2024-01-25 14:41:52 +08:00

RISCVInsertVSETVLI.cpp

[RISCV] Add statistic support for VSETVL insertion pass (#78543)

2024-01-19 08:22:25 +08:00

RISCVInsertWriteVXRM.cpp

[RISCV] Don't emit vxrm writes for vnclip(u).wi with shift of 0. (#76578)

2024-01-02 09:50:06 -08:00

RISCVInstrFormats.td

[RISCV] Move Zimop to RISCVInstrInfoZimop.td (#76392)

2023-12-27 11:19:38 +08:00

RISCVInstrFormatsC.td

…

RISCVInstrFormatsV.td

…

RISCVInstrGISel.td

[RISCV][GISel] Add support for G_IS_FPCLASS in F and D extensions (#72000)

2023-11-22 16:43:20 -08:00

RISCVInstrInfo.cpp

[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)

2024-02-01 17:52:35 -08:00

RISCVInstrInfo.h

[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)

2024-02-01 17:52:35 -08:00

RISCVInstrInfo.td

[RISCV] Add XTheadMac patterns for -riscv-experimental-rv64-legal-i32.

2024-02-03 19:37:46 -08:00

RISCVInstrInfoA.td

[RISCV][MC] Add experimental support of Zaamo and Zalrsc

2024-01-25 17:03:25 +08:00

RISCVInstrInfoC.td

[RISCV] Add CompressPat for c.beqz/bnez with X0 in the first operand. (#69042)

2023-10-14 08:12:46 -07:00

RISCVInstrInfoD.td

[RISCV] Refactor GPRF64 register class to make it usable for Zacas. (#77408)

2024-01-09 09:21:27 -08:00

RISCVInstrInfoF.td

[RISCV][NFC] Rename RISCVISD::FPCLASS to RISCVISD::FCLASS

2023-11-22 16:24:05 -08:00

RISCVInstrInfoM.td

[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)

2023-11-01 09:36:41 -07:00

RISCVInstrInfoV.td

[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)

2023-10-08 14:13:08 +08:00

RISCVInstrInfoVPseudos.td

[RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (#71501)

2024-01-16 13:36:24 +07:00

RISCVInstrInfoVSDPatterns.td

[RISCV][ISel] Use vaaddu with rounding mode rnu for ISD::AVGCEILU. (#77473)

2024-01-10 12:08:16 +09:00

RISCVInstrInfoVVLPatterns.td

[RISCV][ISel] Remove redundant vmerge for the vwadd. (#78403)

2024-01-27 20:03:32 +09:00

RISCVInstrInfoXCV.td

[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (#74993)

2023-12-17 19:29:40 +08:00

RISCVInstrInfoXSf.td

[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407)

2024-01-26 11:15:53 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Add XTheadMac patterns for -riscv-experimental-rv64-legal-i32.

2024-02-03 19:37:46 -08:00

RISCVInstrInfoXVentana.td

…

RISCVInstrInfoZa.td

[RISCV][MC] Add MC layer support for the experimental zabha extension (#80005)

2024-01-31 17:06:43 +08:00

RISCVInstrInfoZalasr.td

[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)

2024-02-01 10:58:21 -08:00

RISCVInstrInfoZb.td

[RISCV] Add i32 zext.h pattern for -riscv-experimental-rv64-legal-i32.

2024-02-04 12:39:13 -08:00

RISCVInstrInfoZc.td

[RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061)

2023-12-27 09:11:34 +08:00

RISCVInstrInfoZcmop.td

[RISCV] Add MC layer support for Zicfiss. (#66043)

2023-12-30 15:40:20 +08:00

RISCVInstrInfoZfa.td

[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633)

2023-10-19 14:55:33 -07:00

RISCVInstrInfoZfbfmin.td

[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)

2023-11-01 09:36:41 -07:00

RISCVInstrInfoZfh.td

[RISCV] Combine HasStdExtZfhOrZfhmin and HasStdExtZfhmin. NFC (#78826)

2024-01-22 13:06:37 -08:00

RISCVInstrInfoZicbo.td

[RISCV] Match prefetch address with offset (#66072)

2023-10-20 14:22:48 +08:00

RISCVInstrInfoZicfiss.td

[RISCV] Add MC layer support for Zicfiss. (#66043)

2023-12-30 15:40:20 +08:00

RISCVInstrInfoZicond.td

[RISCV] Graduate Zicond to non-experimental (#79811)

2024-01-29 15:58:54 +00:00

RISCVInstrInfoZimop.td

[RISCV][ISel] Add ISel support for experimental Zimop extension (#77089)

2024-01-29 15:24:00 -08:00

RISCVInstrInfoZk.td

[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)

2023-10-08 14:13:08 +08:00

RISCVInstrInfoZvfbf.td

…

RISCVInstrInfoZvk.td

[RISCV][NFC] Remove unused methods of tuimm5 (#79680)

2024-01-29 09:54:34 +08:00

RISCVISelDAGToDAG.cpp

[Target] Use getConstantOperand (NFC)

2024-01-28 18:03:38 -08:00

RISCVISelDAGToDAG.h

[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407)

2024-01-26 11:15:53 +08:00

RISCVISelLowering.cpp

[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.

2024-02-04 23:15:58 -08:00

RISCVISelLowering.h

[RISCV] Remove unused RISCVISD opcodes. NFC

2024-01-30 20:46:01 -08:00

RISCVMachineFunctionInfo.cpp

…

RISCVMachineFunctionInfo.h

…

RISCVMacroFusion.td

[RISCV] Use TableGen-based macro fusion (#72224)

2024-01-25 17:10:49 +08:00

RISCVMakeCompressible.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVMergeBaseOffset.cpp

[RISCV] Merge ADDI with X0 into base offset (#78940)

2024-01-23 09:57:05 +08:00

RISCVMoveMerger.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVOptWInstrs.cpp

[RISCV] Rework isSignExtendingOpW to store Register in the worklist.

2024-02-03 23:40:09 -08:00

RISCVPostRAExpandPseudoInsts.cpp

[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)

2023-11-09 15:15:23 +08:00

RISCVProcessors.td

[RISCV] Add TuneNoSinkSplatOperands to sifive-p670 (#79492)

2024-01-26 11:05:04 -05:00

RISCVPushPopOptimizer.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVRedundantCopyElimination.cpp

…

RISCVRegisterInfo.cpp

[RISCV] Allow VCIX with SE to reorder (#77049)

2024-01-24 11:30:12 +08:00

RISCVRegisterInfo.h

…

RISCVRegisterInfo.td

[RISCV] Allow VCIX with SE to reorder (#77049)

2024-01-24 11:30:12 +08:00

RISCVRVVInitUndef.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVSchedRocket.td

[RISCV][MC] Add MC layer support for the experimental zabha extension (#80005)

2024-01-31 17:06:43 +08:00

RISCVSchedSiFive7.td

[RISCV][MC] Add MC layer support for the experimental zabha extension (#80005)

2024-01-31 17:06:43 +08:00

RISCVSchedSiFiveP400.td

[RISCV][MC] Add MC layer support for the experimental zabha extension (#80005)

2024-01-31 17:06:43 +08:00

RISCVSchedSyntacoreSCR1.td

[RISCV][MC] Add MC layer support for the experimental zabha extension (#80005)

2024-01-31 17:06:43 +08:00

RISCVSchedule.td

[RISCV][MC] Add MC layer support for the experimental zabha extension (#80005)

2024-01-31 17:06:43 +08:00

RISCVScheduleV.td

[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

2023-12-04 17:21:02 -05:00

RISCVScheduleZb.td

…

RISCVSubtarget.cpp

[RISCV] Use TableGen-based macro fusion (#72224)

2024-01-25 17:10:49 +08:00

RISCVSubtarget.h

[RISCV] Use TableGen-based macro fusion (#72224)

2024-01-25 17:10:49 +08:00

RISCVSystemOperands.td

[RISCV] Add srmcfg CSR from Ssqosid extension. (#79914)

2024-02-01 11:59:13 -08:00

RISCVTargetMachine.cpp

[RISCV] Use TableGen-based macro fusion (#72224)

2024-01-25 17:10:49 +08:00

RISCVTargetMachine.h

…

RISCVTargetObjectFile.cpp

[llvm] Indirect symbol replacement with GOTPCREL for aarch64 and risc… (#78003)

2024-01-16 15:32:35 -08:00

RISCVTargetObjectFile.h

[llvm] Indirect symbol replacement with GOTPCREL for aarch64 and risc… (#78003)

2024-01-16 15:32:35 -08:00

RISCVTargetTransformInfo.cpp

Revert "[RISCV] Refine cost on Min/Max reduction" (#80340)

2024-02-01 13:09:07 -08:00

RISCVTargetTransformInfo.h

[TTI]Add support for strided loads/stores.

2024-02-01 16:07:38 -05:00