Yeaseen 96c723374a [llvm] Remove br i1 undef from some llvm/test/CodeGen tests (#128272)

2025-02-23 09:23:33 +00:00

..

AArch64

[llvm] Remove br i1 undef from some llvm/test/CodeGen tests (#128272)

2025-02-23 09:23:33 +00:00

AMDGPU

[llvm] Remove br i1 undef from some llvm/test/CodeGen tests (#128272)

2025-02-23 09:23:33 +00:00

ARC

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ARM

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AVR

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BPF

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CSKY

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DirectX

[HLSL] Add more tests to root signature metadata extraction (#127283)

2025-02-18 11:40:29 -08:00

Generic

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Hexagon

[Hexagon] Explicitly truncate constant in UAddSubO (#127360)

2025-02-17 09:30:48 -06:00

Inputs

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Lanai

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LoongArch

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

M68k

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Mips

[Mips] Reserve hardware register HWR2 (#127775)

2025-02-20 20:53:30 +08:00

MIR

[NVPTX] Remove redundant addressing mode instrs (#128044)

2025-02-20 14:51:06 -08:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX][InferAS] assume alloca instructions are in local AS (#121710)

2025-02-21 14:32:54 -08:00

PowerPC

[NFC] add a pre-commit test case for patch #127121 that hoists xxsplitib out of loop (#127701)

2025-02-21 10:29:52 -05:00

RISCV

[RISCV][VLOpt] Put vmclr/vmset back in the RISCVVPseudo table. (#128293)

2025-02-22 15:30:35 -08:00

SPARC

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

SPIRV

[SPIR-V] Initial implementation of SPV_INTEL_long_composites (#126545)

2025-02-20 16:09:06 +01:00

SystemZ

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Thumb

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Thumb2

PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)

2025-02-22 09:16:14 +07:00

VE

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

WebAssembly

[WebAssembly] Enable interleaved memory accesses (#125696)

2025-02-17 09:09:52 +00:00

WinCFGuard

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WinEH

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X86

[llvm] Remove br i1 undef from some llvm/test/CodeGen tests (#128272)

2025-02-23 09:23:33 +00:00

XCore

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Xtensa

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