474f5d2aef
These cannot be detected by reading the ID_AA64ISAR1_EL1 register since their corresponding bitfields are hidden. Additionally the instructions that these features enable are unusable from EL0. ACLE: https://github.com/ARM-software/acle/pull/382
56 lines
2.4 KiB
C
56 lines
2.4 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 5
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
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// Priority biskmasks after feature dependency expansion:
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//
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// MSB LSB
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//
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// sme2 | wfxt | sme | bf16 | | | fp16 | simd | fp
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// -----+------+-----+------+-------+------+------+------+---
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// sme2 | | sme | bf16 | rcpc2 | rcpc | fp16 | simd | fp
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//
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// Dependencies should not affect priorities, since a
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// feature can only depend on lower priority features:
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// https://github.com/ARM-software/acle/pull/376
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__attribute__((target_version("sme2+wfxt"))) int fn(void);
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__attribute__((target_version("sme2+rcpc2"))) int fn(void);
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__attribute__((target_version("default"))) int fn(void) { return 0; }
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int call() { return fn(); }
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// CHECK-LABEL: define dso_local i32 @fn.default(
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// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: ret i32 0
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//
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//
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// CHECK-LABEL: define dso_local i32 @call(
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// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[CALL:%.*]] = call i32 @fn()
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// CHECK-NEXT: ret i32 [[CALL]]
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//
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//
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// CHECK-LABEL: define weak_odr ptr @fn.resolver() comdat {
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// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 162133984766132992
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 162133984766132992
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
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// CHECK: [[RESOLVER_RETURN]]:
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// CHECK-NEXT: ret ptr @fn._Msme2Mwfxt
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// CHECK: [[RESOLVER_ELSE]]:
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 144119586269233920
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 144119586269233920
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// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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// CHECK-NEXT: br i1 [[TMP7]], label %[[RESOLVER_RETURN1:.*]], label %[[RESOLVER_ELSE2:.*]]
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// CHECK: [[RESOLVER_RETURN1]]:
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// CHECK-NEXT: ret ptr @fn._Mrcpc2Msme2
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// CHECK: [[RESOLVER_ELSE2]]:
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// CHECK-NEXT: ret ptr @fn.default
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//
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