84fa1755a5
The FEAT_SPEv1p2 feature (known to LLVM as FeatureSPE_EEF and +spe-eef) was incorrectly marked as a required feature of Armv8.7-A (and later), which is incorrect because it is optional, and some CPUs do not implement it. This moves it to the default features list, so that it is still enabled by -march=armv8.7-a, but can be configured individually for each processor. For Cortex-A520 and Cortex-A520AE, I've checked that these do not have any of the FEAT_SPE* features, so updated the tests accordingly. All other Arm-designed v8.7A+ and v9.2A+ CPUs should continue to have it enabled. For Ampere1B and Fujitsu Monaka, these CPUs do not have the feature, so I've removed it from their tests. For Apple M4, I haven't found any reference for whether that CPU should have this feature, so I've added it to the CPU definition to avoid this being a functional change.
226 lines
11 KiB
C
226 lines
11 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-globals
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// RUN: %clang_cc1 -triple aarch64 -emit-llvm %s -o - | FileCheck %s
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__attribute__((target("arch=armv8.2-a")))
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// CHECK-LABEL: define {{[^@]+}}@v82
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// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v82() {}
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__attribute__((target("arch=armv8.2-a+sve")))
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// CHECK-LABEL: define {{[^@]+}}@v82sve
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// CHECK-SAME: () #[[ATTR1:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v82sve() {}
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__attribute__((target("arch=armv8.2-a+sve2")))
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// CHECK-LABEL: define {{[^@]+}}@v82sve2
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// CHECK-SAME: () #[[ATTR2:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v82sve2() {}
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__attribute__((target("arch=armv8.2-a+sve+sve2")))
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// CHECK-LABEL: define {{[^@]+}}@v82svesve2
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// CHECK-SAME: () #[[ATTR2]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v82svesve2() {}
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__attribute__((target("arch=armv8.6-a+sve2")))
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// CHECK-LABEL: define {{[^@]+}}@v86sve2
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// CHECK-SAME: () #[[ATTR3:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v86sve2() {}
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__attribute__((target("cpu=cortex-a710")))
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// CHECK-LABEL: define {{[^@]+}}@a710
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// CHECK-SAME: () #[[ATTR4:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void a710() {}
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__attribute__((target("tune=cortex-a710")))
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// CHECK-LABEL: define {{[^@]+}}@tunea710
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// CHECK-SAME: () #[[ATTR5:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void tunea710() {}
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__attribute__((target("cpu=generic")))
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// CHECK-LABEL: define {{[^@]+}}@generic
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// CHECK-SAME: () #[[ATTR6:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void generic() {}
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__attribute__((target("tune=generic")))
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// CHECK-LABEL: define {{[^@]+}}@tune
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// CHECK-SAME: () #[[ATTR7:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void tune() {}
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__attribute__((target("cpu=neoverse-n1,tune=cortex-a710")))
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// CHECK-LABEL: define {{[^@]+}}@n1tunea710
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// CHECK-SAME: () #[[ATTR8:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void n1tunea710() {}
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__attribute__((target("sve,tune=cortex-a710")))
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// CHECK-LABEL: define {{[^@]+}}@svetunea710
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// CHECK-SAME: () #[[ATTR9:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void svetunea710() {}
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__attribute__((target("+sve,tune=cortex-a710")))
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// CHECK-LABEL: define {{[^@]+}}@plussvetunea710
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// CHECK-SAME: () #[[ATTR9]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void plussvetunea710() {}
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__attribute__((target("cpu=neoverse-v1,+sve2")))
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// CHECK-LABEL: define {{[^@]+}}@v1plussve2
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// CHECK-SAME: () #[[ATTR10:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v1plussve2() {}
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__attribute__((target("cpu=neoverse-v1+sve2")))
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// CHECK-LABEL: define {{[^@]+}}@v1sve2
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// CHECK-SAME: () #[[ATTR10]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v1sve2() {}
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__attribute__((target("cpu=neoverse-v1,+nosve")))
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// CHECK-LABEL: define {{[^@]+}}@v1minussve
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// CHECK-SAME: () #[[ATTR11:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v1minussve() {}
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__attribute__((target("cpu=neoverse-v1,no-sve")))
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// CHECK-LABEL: define {{[^@]+}}@v1nosve
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// CHECK-SAME: () #[[ATTR11]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v1nosve() {}
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__attribute__((target("cpu=neoverse-v1+nosve")))
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// CHECK-LABEL: define {{[^@]+}}@v1msve
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// CHECK-SAME: () #[[ATTR11]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void v1msve() {}
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__attribute__((target("+sve")))
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// CHECK-LABEL: define {{[^@]+}}@plussve
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// CHECK-SAME: () #[[ATTR12:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void plussve() {}
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__attribute__((target("+sve+nosve2")))
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// CHECK-LABEL: define {{[^@]+}}@plussveplussve2
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// CHECK-SAME: () #[[ATTR12]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void plussveplussve2() {}
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__attribute__((target("sve,no-sve2")))
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// CHECK-LABEL: define {{[^@]+}}@plussveminusnosve2
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// CHECK-SAME: () #[[ATTR12]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void plussveminusnosve2() {}
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__attribute__((target("+fp16")))
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// CHECK-LABEL: define {{[^@]+}}@plusfp16
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// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void plusfp16() {}
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__attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2")))
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// CHECK-LABEL: define {{[^@]+}}@all
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// CHECK-SAME: () #[[ATTR14:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void all() {}
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__attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2,branch-protection=standard")))
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// CHECK-LABEL: define {{[^@]+}}@allplusbranchprotection
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// CHECK-SAME: () #[[ATTR15:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void allplusbranchprotection() {}
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__attribute__((target("+nosimd")))
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// CHECK-LABEL: define {{[^@]+}}@plusnosimd
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// CHECK-SAME: () #[[ATTR16:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void plusnosimd() {}
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__attribute__((target("no-simd")))
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// CHECK-LABEL: define {{[^@]+}}@nosimd
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// CHECK-SAME: () #[[ATTR16]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void nosimd() {}
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// This isn't part of the standard interface, but test that -arch features should not apply anything else.
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__attribute__((target("no-v9.3a")))
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// CHECK-LABEL: define {{[^@]+}}@minusarch
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// CHECK-SAME: () #[[ATTR17:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void minusarch() {}
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__attribute__((target("cpu=apple-m4")))
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// CHECK-LABEL: define {{[^@]+}}@applem4
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// CHECK-SAME: () #[[ATTR18:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret void
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//
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void applem4() {}
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//.
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// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
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// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
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// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
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// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
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// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve-bitperm,+sve2,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" }
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// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" }
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// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
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// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" }
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// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
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// CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" }
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// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
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// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
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// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
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// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" }
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// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
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// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
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// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
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// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+spe-eef,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" }
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//.
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// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
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// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
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//.
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